M68HC05 datasheet(84/302 Pages) FREESCALE

84 / 302 page

Freescale

6-12

MC68HC05B6

Rev. 4.1

SERIAL COMMUNICATIONS INTERFACE

CPOL – Clock polarity

This bit allows the user to select the polarity of the clocks to be sent to the SCLK pin. It works in

conjunction with the CPHA bit to produce the desired clock-data relation (see Figure 6-9 and

Figure 6-10).

1 (set)

–

Steady high value at SCLK pin outside transmission window.

0 (clear) –

Steady low value at SCLK pin outside transmission window.

This bit should not be manipulated while the transmitter is enabled.

CPHA – Clock phase

This bit allows the user to select the phase of the clocks to be sent to the SCLK pin. This bit works

in conjunction with the CPOL bit to produce the desired clock-data relation (see Figure 6-9 and

Figure 6-10).

1 (set)

–

SCLK clock line activated at beginning of data bit.

0 (clear) –

SCLK clock line activated in middle of data bit.

This bit should not be manipulated while the transmitter is enabled.

Figure 6-9 SCI data clock timing diagram (M=0)

Idle or preceding

transmission

clock

Stop

Start

LSB

data

M = 0 (8 data bits)

Idle or next

LBCL bit controls last data clock

transmission

clock

Start

Stop

234

MSB

(CPOL = 0, CPHA = 0)

(CPOL = 0, CPHA = 1)

(CPOL = 1, CPHA = 0)

(CPOL = 1, CPHA = 1)

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