LD7530 datasheet(11/19 Pages) LEADTREND

11 / 19 page

LD7530/LD7530A

Leadtrend Technology Corporation

LD7530&LD7530A-DS-04 December 2007

Internal Slope Compensation

In the conventional application, the problem of the stability is

a critical issue for current mode controlling, when it operates

in higher than 50% of the duty-cycle. As UC384X, It takes

slope compensation from injecting the ramp signal of the

RT/CT pin through a coupling capacitor. It therefore requires

no extra design for the LD7530/LD7530A since it has

integrated it already.

On/Off Control

The LD7530/LD7530A can be turned off by pulling COMP

pin lower than 1.2V.

The gate output pin of the

LD7530/LD7530A will be disabled immediately under such

condition. The off-mode can be released when the pull-low

signal is removed.

Dual-Oscillator Green-Mode Operation

There are many different topologies has been implemented

in different chips for the green-mode or power saving

requirements such as “burst-mode control”, “skipping-cycle

mode”, “variable off-time control “…etc. The basic operation

theory of all these approaches intended to reduce the

switching cycles under light-load or no-load condition either

by skipping some switching pulses or reduce the switching

frequency.

What LD7530/LD7530A use to implement the power-saving

operation is Leadtrend Technology’s own IP. By using this

dual-oscillator control, the green-mode frequency can be

well controlled and further to avoid the generation of audible

noise.

OVP (Over Voltage Protection) on Vcc

The VGS ratings of the nowadays power MOSFETs are often

limited up to max. 30V. To prevent the VGS from the fault

condition, LD7530/LD7530A are implemented an OVP

function on Vcc. Whenever the Vcc voltage is higher than

the OVP threshold voltage, the output gate drive circuit will

be shutdown simultaneously thus to stop the switching of

the power MOSFET until the next UVLO(on).

The Vcc OVP function in LD7530/LD7530A is an

auto-recovery type protection.

If the OVP condition,

usually caused by the feedback loop opened, is not

released, the Vcc will tripped the OVP level again and

re-shutdown the output. The Vcc is working as a hiccup

mode. The figure 18 shows its operation.

On the other hand, if the OVP condition is removed, the Vcc

level will get back to normal level and the output will

automatically return to the normal operation.

Fig. 18

Over Load Protection (OLP)

To protect the circuit from being damaged under over load

condition or short condition, a smart OLP function is

implemented in the LD7530/LD7530A. The figure 19 shows

the waveforms of the OLP operation. In this case, the

feedback system will force the voltage loop proceed toward

the saturation and then pull up the voltage on COMP pin

(VCOMP). Whenever the VCOMP trips up to the OLP threshold

5V and stays longer than the OLP delay time, the protection

will activate and then turn off the gate output to stop the

switching of power circuit. The OLP delay time, set by CT

pin, is to prevent the false trigger from the power-on and

turn-off transient. Higher CT value will generate longer OLP

delay time. For the recommended CT value, the OLP delay

time is around 90mS when CT=0.1

μF and will be around

50mS if CT=0.047

μF.

By such protection mechanism, the average input power

can be reduced to very low level so that the component

temperature and stress can be controlled within the safe

operating area.

LD7530 Datasheet(PDF) 11 Page - Leadtrend Technology

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