7.3.3 Receiver Detect State Machine

The DS320PR410 deploys an Rx detect state machine that governs the Rx detection cycle as defined in the

PCI express specifications. At power up or after a manual PD toggle the redriver determines whether or not

a valid PCI express termination is present at the far end receiver. The RX_DET pin of DS320PR410 provides

additional flexibility for system designers to appropriately set the device in desired mode as provided in Table

7-3. If multiple DS320PR410 devices are used for a same PCI express link, then the PD pins from different

devices can be shorted and driven together. For most applications the RX_DET pin can be left floating for default

settings. In SMBus/I2C mode each channel can be configured independently.

Table 7-3. Receiver Detect State Machine Settings

PD

RX_DET

Rx Impedance

COMMENTS

L

L0

Always 50 Ω

PCI Express Rx detection state machine is disabled. Recommended

for non PCIe interface use case where the DS320PR410 is used as

buffer with equalization.

L

L1

Pre Detect: Hi-Z

Post Detect: 50 Ω.

Outputs polls until 3 consecutive valid detections

L

L2

Pre Detect: Hi-Z

Post Detect: 50 Ω.

Outputs polls until 2 consecutive valid detections

L

L3

NA

Reserved

L

L4 (Float)

Pre Detect: Hi-Z

Post Detect: 50 Ω.

Tx polls every

≅150 µs until valid termination is detected. Rx

impedance held at Hi-Z until detection. Reset by asserting PD high

for 200 µs then low.

H

X

Hi-Z

Reset Channels 0-3 signal path and set their Rx impedance to Hi-Z

In PCIe applications, the PD pin can be connected to PCIe sideband signals PERST# with inverted polarity or

one or more appropriate PRSNTx# signals to achieve the desired RX detect functionality.

7.4 Device Functional Modes

7.4.1 Active PCIe Mode

In pin mode, the RX_DET = L1/L2/L4 sets the device in normal operation with PCIe state machine enabled.

See RX Detect Control Registers in i2c mode. In the active PCIe mode, the PD pin is driven low in a system

(for example, by PCIE connector PRSNTx# or fundamental reset PERST# signal). In active PCIe mode, the

DS320PR410 redrives and equalizes PCIe Rx or Tx signals to provide better signal integrity.

7.4.2 Active Buffer Mode

In pin mode, the RX_DET = L0 sets the device in normal operation with PCIe state machine disabled. For more

information, see RX Detect Control Registers in I2c mode. The active buffer mode is recommended for non-PCIe

use cases, where the device is working as a buffer to provide linear equalization to improve signal integrity.

7.4.3 Standby Mode

The pin setting PD = H puts the device in standby mode. In this mode, the device is in standby mode conserving

power.

7.5 Programming

7.5.1 Pin mode

The DS320PR410 can be fully configured through pin-strap pins. In this mode, the device uses 2-level and

5-level pins for device control and signal integrity optimum settings.

7.5.1.1 Five-Level Control Inputs

The DS320PR410 has five (EQ0, EQ1, GAIN, MODE, and RX_DET) 5-level input pins that are used to control

the configuration of the device. These 5-level inputs use a resistor divider to help set the 5 valid levels and

provide a wider range of control settings. External resistors must be of 10% tolerance or better. The EQ0, EQ1,

DS320PR410

SNLS739 – OCTOBER 2023

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