8.2.1 PCIe Reach Extension – x16 Lane Configuration

The DS320PR410 can be used in server or motherboard applications to boost transmit and receive signals to

increase the reach of the host or root complex processor to PCI Express slots or connectors. The following

sections outline detailed procedures and design requirements for a typical PCIe x16 lane configuration; however,

the design recommendations can be used in any lane configuration.

8.2.1.1 Design Requirements

As with any high-speed design, there are many factors which influence the overall performance. The following

list indicates critical areas for consideration during design.

• Use 85 Ω impedance traces when interfacing with PCIe CEM connectors. Length matching on the P and N

traces should be done on the single-end segments of the differential pair.

• Use a uniform trace width and trace spacing for differential pairs.

• Place AC-coupling capacitors near the receiver end of each channel segment to minimize reflections.

• For PCIe Gen 3.0, 4.0, and 5.0, AC-coupling capacitors of 220 nF are recommended. Set the maximum

body size to 0402 and add a cutout void on the GND plane below the landing pad of the capacitor to reduce

parasitic capacitance to GND.

• Back-drill connector vias and signal vias to minimize stub length.

• Use reference plane vias for a low inductance path for the return current.

8.2.1.2 Detailed Design Procedure

In PCIe Gen 3.0, 4.0, and 5.0 applications, the specification requires Rx-Tx (of root-complex and endpoint) link

training to establish and optimize signal conditioning settings at 8 Gbps, 16 Gbps, and 32 Gbps, respectively. In

link training, the Rx partner requests a series of FIR – preshoot and de-emphasis coefficients (10 Presets) from

the Tx partner. The Rx partner includes 7-levels of CTLE followed by a single tap DFE. The link training would

pre-condition the signal, with an equalized link between the root-complex and endpoint resulting an optimized

link. Note that there is no link training in PCIe Gen 1.0 (2.5 Gbps) or PCIe Gen 2.0 (5.0 Gbps) applications.

For operation in Gen 3.0, 4.0, and 5.0 links, the DS320PR410 is designed with linear data-path to pass the

Tx Preset signaling (by root complex and end point) onto the Rx (of root complex and end point) for the PCIe

Gen 3.0, 4.0, or 5.0 link to train and optimize the equalization settings. The linear redriver DS320PR410 helps

extend the PCB trace reach distance by boosting the attenuated signals with its equalization, which allows the

user to recover the signal by the downstream Rx more easily. The device must be placed in between the Tx and

Rx (of root complex and end point) in such a way that both Rx and Tx signal swing stays within the linearity

range of the device. Adjustments to the DS320PR410 EQ setting should be performed based on the channel

loss to optimize the eye opening in the Rx partner. The available EQ gain settings are provided in Table 7-1. For

most PCIe systems, the default flat gain setting 0 dB (GAIN = floating) would be sufficient. However, a flat gain

attenuation can be utilized to apply extra equalization when needed to keep the data-path linear.

The DS320PR410 can be optimized for a given system utilizing its three configuration modes – Pin mode,

SMBus/I2C Primary mode, and SMBus/I2C Secondary mode. In SMBus/I2C modes the SCL and SDA pins must

be pulled up to a 3.3 V supply with a pull-up resistor. The value of the resistor depends on total bus capacitance.

4.7 kΩ is a good first approximation for a bus capacitance of 10 pF.

In PCIe applications PD pin can be connected to PCIe sideband signals PERST# with inverted polarity or one or

more appropriate PRSNTx# signals to achieve desired RX detect functionality.

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DS320PR410

SNLS739 – OCTOBER 2023

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