| Electronic Components Datasheet Search |
|
ADC34RF52 Datasheet(PDF) 45 Page - Texas Instruments |
|
|
|||||||||||||||||||||||||||||
ADC34RF52 Datasheet(HTML) 45 Page - Texas Instruments |
|
45 / 105 page ![]() 6.3.6.2 JESD204B Frame Assembly The JESD204B standard defines the following parameters: • L: number of lanes per link • M: number of converters per device • F: number of octets per frame clock period • S: number of samples per frame 6.3.6.2.1 JESD204B Frame Assembly in Bypass Mode Table 6-28 lists the available JESD204B formats and corresponding valid sampling rate ranges for the ADC34RF5x. The sampling rates are limited by the minimum and maximum SERDES line rate as well as ADC sampling clock frequencies. The JESD204B frame assembly for the different lanes is shown in Table 6-29. Table 6-28. JESD Mode Options: Bypass Mode DECIMATION SETTING D (complex) OUTPUT RESOLUTION (Bits) L M F S MIN FS (Gsps) MAX FS (Gsps) RATIO [fSERDES/FS] Bypass 12(1) 8 4 8 10 0.5 1.5 8 14 8 4 2 2 0.5 1.3 10 14 4 4 2 1 0.5 0.65 20 (1) In full rate output, the two LSBs are truncated to a 12-bit output. Table 6-29. JESD Sample Frame Assembly: Bypass Mode OUTPUT LANE LMFS = 84810 LMFS = 8422 LMFS = 4421 DOUT0 A0[11:4] A0[3:0], A1[11:8] A1[7:0] A2[11:4] A2[3:0], A3[11:8] A3[7:0] A4[11:4] A4[3:0], 0000 A0[13:6] A0[5:0], 00 A0[13:6] A0[5:0], 00 DOUT1 A5[11:4] A5[3:0], A6[11:8] A6[7:0] A7[11:4] A7[3:0], A8[11:8] A8[7:0] A9[11:4] A9[3:0], 0000 A1[13:6] A1[5:0], 00 B0[13:6] B0[5:0], 00 DOUT2 B0[11:4] B0[3:0], B1[11:8] B1[7:0] B2[11:4] B2[3:0], B3[11:8] B3[7:0] B4[11:4] B4[3:0], 0000 B0[13:6] B0[5:0], 00 C0[13:6] C0[5:0], 00 DOUT3 B5[11:4] B5[3:0], B6[11:8] B6[7:0] B7[11:4] B7[3:0], B8[11:8] B8[7:0] B9[11:4] B9[3:0], 0000 B1[13:6] B1[5:0], 00 D0[13:6] D0[5:0], 00 DOUT4 C0[11:4] C0[3:0], C1[11:8] C1[7:0] C2[11:4] C2[3:0], C3[11:8] C3[7:0] C4[11:4] C4[3:0], 0000 C0[13:6] C0[5:0], 00 DOUT5 C5[11:4] C5[3:0], C6[11:8] C6[7:0] C7[11:4] C7[3:0], C8[11:8] C8[7:0] C9[11:4] C9[3:0], 0000 C1[13:6] C1[5:0], 00 DOUT6 D0[11:4] D0[3:0], D1[11:8] D1[7:0] D2[11:4] D2[3:0], D3[11:8] D3[7:0] D4[11:4] D4[3:0], 0000 D0[13:6] D0[5:0], 00 DOUT7 D5[11:4] D5[3:0], D6[11:8] D6[7:0] D7[11:4] D7[3:0], D8[11:8] D8[7:0] D9[11:4] D9[3:0], 0000 D1[13:6] D1[5:0], 00 www.ti.com ADC34RF55 SBAS988 – NOVEMBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 45 Product Folder Links: ADC34RF55 |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |