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ADC34RF52 Datasheet(PDF) 73 Page - Texas Instruments

Part # ADC34RF52
Description  ADC34RF55 Quad Channel 14-bit 3-GSPS RF Sampling Data Converter
PDF  105 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

ADC34RF52 Datasheet(HTML) 73 Page - Texas Instruments

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Figure 6-79. Register 0x89/8A/8B/8C/8D/8E/8F/90 (JESD page)
7
6
5
4
3
2
1
0
TX EMPH
DOUT1 [0]
TX EMPH DOUT0 [5:0]
0
0
0
0
TX EMPH DOUT1 [5:1]
TX EMPH
DOUT3 [0]
TX EMPH DOUT2 [5:0]
0
0
0
0
TX EMPH DOUT3 [5:1]
TX EMPH
DOUT5 [0]
TX EMPH DOUT4 [5:0]
0
0
0
0
TX EMPH DOUT5 [5:1]
TX EMPH
DOUT7 [0]
TX EMPH DOUT6 [5:0]
0
0
0
0
TX EMPH DOUT7 [5:1]
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Table 6-80. Register 0x89/8A/8B/8C/8D/8E/8F/90 Field Descriptions
Bit
Field
Type
Reset
Description
7-5,0
0
R/W
0
Must write 0
6-1
TX EMPH DOUT0/2/4/6 [5:0]
R/W
000000
These bits select the amount of de-emphasis for the JESD
output transmitter. The de-emphasis value in dB is measured
as the ratio between the peak value after the signal transition to
the settled value of the voltage in one bit period.
0: 0 dB
1: –1 dB
3: –2 dB
7: –4.1 dB
15: –6.2 dB
31: –8.2 dB
63: –11.5 dB
4-0,7
TX EMPH DOUT1/3/5/7 [5:0]
R/W
000000
Figure 6-80. Register 0x9D/9E (JESD page)
7
6
5
4
3
2
1
0
PD DOUT7
[0,1]
PD DOUT6
[0,1]
PD DOUT5
[0,1]
PD DOUT4
[0,1]
PD DOUT3
[0,1]
PD DOUT2
[0,1]
PD DOUT1
[0,1]
PD DOUT0
[0,1]
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Table 6-81. Register 0x9D/9E Field Descriptions
Bit
Field
Type
Reset
Description
7-0
PD DOUTx [0,1]
R/W
0
Register 0x9D and 0x9E allow power down of individual serdes
output lanes. Register 0x9D (PD DOUTx [0]) covers the output
driver, 0x9E (PD DOUTx [1]) covers the associated internal
high-speed data clock.
0: Output lane enabled
1: Output lane powered down
www.ti.com
ADC34RF55
SBAS988 – NOVEMBER 2023
Copyright © 2023 Texas Instruments Incorporated
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Product Folder Links: ADC34RF55



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