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ADC34RF52 Datasheet(PDF) 71 Page - Texas Instruments

Part # ADC34RF52
Description  ADC34RF55 Quad Channel 14-bit 3-GSPS RF Sampling Data Converter
PDF  105 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

ADC34RF52 Datasheet(HTML) 71 Page - Texas Instruments

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Figure 6-73. Register 0x53 (JESD page)
7
6
5
4
3
2
1
0
SCR EN
0
0
0
0
0
0
0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Table 6-74. Register 0x53 Field Descriptions
Bit
Field
Type
Reset
Description
7
SCR EN
R/W
0
Enables scrambling of the JESD output data
0: Output scrambling disabled
1: Output scrambling enabled
6-0
0
R/W
0
Must write 0
Figure 6-74. Register 0x5C (JESD page)
7
6
5
4
3
2
1
0
F in ILA
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Table 6-75. Register 0x5C Field Descriptions
Bit
Field
Type
Reset
Description
7-0
F in ILA
R/W
0
These bits set F in the ILA sequence. Register value is actual F
value -1 (0x01 = F(2)).
Figure 6-75. Register 0x5D (JESD page)
7
6
5
4
3
2
1
0
K in ILA
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Table 6-76. Register 0x5D Field Descriptions
Bit
Field
Type
Reset
Description
7-0
K in ILA
R/W
0
These bits set K in the ILA sequence. Register value is actual K
value -1 (0x0F = K(15))
Figure 6-76. Register 0x7A (JESD page)
7
6
5
4
3
2
1
0
JESD LANE POL INV
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Table 6-77. Register 0x7A Field Descriptions
Bit
Field
Type
Reset
Description
7-0
JESD LANE POL INV
R/W
00000000
This register inverts the polarity of the individual SERDES output
lanes. Register bit D0 corresponds to SERDES lane DOUT0, D1
to DOUT1, and so on
0: Output polarity as is
1: Output polarity inverted
www.ti.com
ADC34RF55
SBAS988 – NOVEMBER 2023
Copyright © 2023 Texas Instruments Incorporated
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Product Folder Links: ADC34RF55



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