VC0736 datasheet(108/127 Pages) NEXTCHIP

108 / 127 page

NVP6124

Data sheet

02.11.2015 (REV 0.2)

106/125

4-CH AHD2.0 RX and 9-CH Audio Codec



Registers to Control Video Output Port Enable

ADDRESS

BITS

VALUE

DESCRIPTION

Bank

Addr

30P

25P

0xCA

VCLK_4_EN

[7]

0xFF

VCLK_x_EN

: Video Output Port_x CLK Enable (x = VDO output port number)

VCLK_3_EN

[6]

VCLK_2_EN

[5]

Disable

Enable

VCLK_1_EN

[4]

VDO_4_EN

[3]

VDO_x_EN

: VDOx DATA Enable (x = VDO output port number)

VDO_3_EN

[2]

VDO_2_EN

[1]

Disable

Enable

VDO_1_EN

[0]



Registers to Select Video Output Clock

ADDRESS

BITS

VALUE

DESCRIPTION

Bank

Addr

30P

25P

0xCC

VCLK1_SEL

[6:4]

0x60

VCLKx_SEL

: Select clock frequency and phase of each port. (x =

Port number)

37.125MHz clock with phase 1

(delay=0ns)

37.125MHz clock with phase 2

(delay≒6.76ns)

37.125MHz clock with phase 3

(delay≒13.47ns)

37.125MHz clock with phase 4

(delay≒26.9ns)

0~3 : Don

’t use When AHD or AFHD MODE

74.125MHz clock with phase 1

(delay=0ns)

74.125MHz clock with phase 2

(delay≒13.47ns)

148.5MHz clock with phase 1

(delay=0ns)

148.5MHz clock with phase 2

(delay≒6.73ns)

0xCD

VCLK2_SEL

0xCE

VCLK3_SEL

0xCF

VCLK4_SEL

0xCC

VCLK_1_DLY_SEL

[3:0]

VCLK_x_DLY_SEL

: Delay the output clock in the unit of ≒ 1ns. Can be delayed up

to ≒ 15ns.

(x =

Port number)

0000

≒ 0ns.

0100

≒ 4ns.

1000

≒ 7ns.

1111

≒ 15ns.

0xCD

VCLK_2_DLY_SEL

0xCE

VCLK_3_DLY_SEL

0xCF

VCLK_4_DLY_SEL

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