Data Sheet

AD45335

THEORY OF OPERATION

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Rev. 0 | 12 of 16

The AD45335 consists of a 32-channel, 14-bit DAC with 200 V

high voltage amplifiers in a single 15 mm × 15 mm chip scale

package ball grid array (CSP_BGA). The output voltage range is

programmable through the REF_IN pin. The output range is 0 V to

50 V when REF_IN = 1 V, and 0 V to 200 V when REF_IN = 4 V.

Communication to the device is through a serial interface operating

at clock rates of up to 30 MHz, which is compatible with digital

signal processing (DSP) and microcontroller interface standards. A

5-bit address and a 14-bit data-word are loaded into the AD45335

input register through the serial interface. The channel address is

decoded, and the data-word is converted into an analog output

voltage for this channel.

At power-on, all the DAC registers are loaded with 0s.

DAC SECTION

The architecture of each DAC channel consists of a resistor

string DAC, followed by an output buffer amplifier operating with

a nominal gain of 50. The voltage at the REF_IN pin provides the

reference voltage for the corresponding DAC. The input coding to

the DAC is straight binary, and the ideal DAC output voltage is

given by

VOUT=50×VREF_IN×D

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where D is the decimal equivalent (0 to 16,383) of the binary code,

which is loaded to the DAC register.

The output buffer amplifier is specified to drive a load of 4 MΩ and

200 pF. The linear output voltage range for the output amplifier is

from 7 V to VPP – 1.5 V. The amplifier output bandwidth is typically

30 kHz, and is capable of sourcing 150 µA and sinking 40 µA.

RESET FUNCTION

The reset function on the AD45335 can be used to reset all nodes

on the device to their power-on reset condition. All the DACs are

loaded with 0s, and all registers are cleared. Take the RESET pin

low to implement the reset function.

SERIAL INTERFACE

The serial interface is controlled by the following pins:

►

SYNC, which is the frame synchronization pin for the serial

interface.

►

SCLK, which is the serial clock input that operates at clock

speeds of up to 30 MHz.

►

DIN, which is the serial data input, and data must be valid upon

the falling edge of SCLK.

To update a single DAC channel, a 19-bit data-word is written to the

AD45335 input register, as shown in Figure 16.

A4 to A0 Bits

The A4 to A0 bits can address any one of the 32 channels. A4 is

the MSB of the address, while A0 is the LSB.

DB13 to DB0 Bits

The DB13 to DB0 bits are used to write a 14-bit data-word into the

addressed DAC register.

Figure 2 is the timing diagram for a serial write to the AD45335. The

serial interface works with both a continuous and a discontinuous

serial clock. The first falling edge of SYNC resets the serial clock

counter to ensure that the correct number of bits are shifted into the

serial shift register. Any further edges on SYNC are ignored until

the correct number of bits are shifted in. After 19 bits are shifted in,

the SCLK is ignored. For another serial transfer to take place, the

counter must be reset by the falling edge of SYNC. The user must

allow 200 ns (minimum) between successive writes.

Figure 16. Serial Data Format