SMSC USB97C201

Page 4

Rev. 11-05-03

DATASHEET

TABLES

Table 1 - USB97C201 Buffer Type Descriptions ..........................................................................................................13

Table 2 - MCU Code Memory Map ..............................................................................................................................14

Table 3 - MCU XData Memory Map .............................................................................................................................15

Table 4 - MCU Block Register Summary......................................................................................................................16

Table 5 - 8051 Core SFR Register Summary...............................................................................................................18

Table 6 - Interrupt 0 Source Register ...........................................................................................................................19

Table 7 - Interrupt 0 Mask ............................................................................................................................................20

Table 8 - Interrupt 1 Source Register ...........................................................................................................................20

Table 9 - Interrupt 1 Mask ............................................................................................................................................21

Table 10 - Device Revision Register ............................................................................................................................21

Table 11 - Device Identification Register......................................................................................................................21

Table 12 - GPIO Direction Register..............................................................................................................................22

Table 13 - GPIO Output Register .................................................................................................................................24

Table 14 - GPIO Input Register....................................................................................................................................24

Table 15 – GPIO Interrupt Status Register (INT4) .......................................................................................................24

Table 16 – GPIO Interrupt Mask Register ....................................................................................................................25

Table 17 - Utility Configuration Register.......................................................................................................................26

Table 18 – SRAM Data Port Register ..........................................................................................................................26

Table 19 – SRAM Address Register 1 .........................................................................................................................27

Table 20 – SRAM Address Register 2 .........................................................................................................................27

Table 21 - MCU Clock Source Select...........................................................................................................................27

Table 22 - Wakeup Source 1 Register (INT2) ..............................................................................................................28

Table 23 - Wakeup Mask 1 Register ............................................................................................................................28

Table 24 –USB Address Register ................................................................................................................................29

Table 25 – SIE Configuration Register.........................................................................................................................29

Table 26 - USB Bus Status Register ............................................................................................................................30

Table 27 – USB Bus Status Mask Register..................................................................................................................30

Table 28 – SIE Status Register ....................................................................................................................................31

Table 29 – SIE Status Mask Register ..........................................................................................................................31

Table 30 – USB Configuration Number Register..........................................................................................................32

Table 31 – Endpoint 0 Receive Control Register .........................................................................................................32

Table 32 – Endpoint 0 Transmit Control Register ........................................................................................................32

Table 33 – Endpoint 1 Receive Control Register .........................................................................................................32

Table 34 – Endpoint 1 Transmit Control Register ........................................................................................................33

Table 35 – Endpoint 2 Control Register .......................................................................................................................33

Table 36 – Endpoint 0 Receive Byte Count Register ...................................................................................................34

Table 37 – Endpoint 0 Transmit Byte Count Register ..................................................................................................35

Table 38 – Endpoint 1 Receive Byte Count Register ...................................................................................................35

Table 39 – Endpoint 1 Transmit Byte Count Register ..................................................................................................35

Table 40 – RAM Buffer Write Byte Count Register A1 .................................................................................................35

Table 41 – RAM BUFFER WRITE Byte Count Register A2 Register...........................................................................35

Table 42 – RAM Buffer Write Byte Count Register B1 .................................................................................................36

Table 43 – RAM Buffer Write Byte Count Register B2 Register...................................................................................36

Table 44 – RAM Buffer Read Byte Count Register A1.................................................................................................36

Table 45 – RAM Buffer Read Byte Count Register A2 Register...................................................................................36

Table 46 – RAM Buffer Read Byte Count Register B1.................................................................................................36

Table 47 – RAM Buffer Read Byte Count Register B2 Register...................................................................................36

Table 48 – NAK Register (INT5) ..................................................................................................................................36

Table 49 – NAK Mask Register ....................................................................................................................................37

Table 50 – USB Error Register.....................................................................................................................................37

Table 51 – MSB ATA Data Register.............................................................................................................................38

Table 52 – LSB ATA Data Register..............................................................................................................................38

Table 53 – ATA Transfer Count Register 0 ..................................................................................................................38

Table 54 – ATA Transfer Count Register 1 ..................................................................................................................38

Table 55 – ATA Transfer Count Register 2 ..................................................................................................................38

Table 56 – ATA Transfer Count Register 3 ..................................................................................................................39

Table 57 –ATA Control Register ..................................................................................................................................39

Table 58 –ATA Ultra DMA Timing Register..................................................................................................................40

Table 59 – IDE Timing Register ...................................................................................................................................40

Table 60 –ATA Slew Rate Control A Register..............................................................................................................42

Table 61 –ATA Slew Rate Control B Register..............................................................................................................42

Table 62 – IDE Transaction Timing..............................................................................................................................46

Table 63 – ULTRA ATA/66 Control Signal Assignments..............................................................................................47

Table 64 –Buffer SRAM Mapping.................................................................................................................................48