USB97C201-MN datasheet(20/59 Pages) SMSC

20 / 59 page

SMSC USB97C201

Page 20

Rev. 11-05-03

DATASHEET

Table 7 - Interrupt 0 Mask

IMR_0

(0x93- RESET=0xFF)

INTERRUPT 0 MASK REGISTER

BIT

NAME

R/W

DESCRIPTION

USB_STAT

R/W

USB Bus System Event interrupt mask

0 = Enable Interrupt

1 = Mask Interrupt

SETUP

R/W

SETUP interrupt mask

0 = Enable Interrupt

1 = Mask Interrupt

Reserved

R/W

Reserved.

ATA_IRQ

R/W

External ATA-66 interrupt input mask

0 = Enable Interrupt

1 = Mask Interrupt

RAMRD_B

R/W

SRAM Buffer B Output Interrupt Mask

0 = Enable Interrupt

1 = Mask Interrupt

RAMRD_A

R/W

SRAM Buffer A Output Interrupt Mask

0 = Enable Interrupt

1 = Mask Interrupt

RAMWR_B

R/W

SRAM Buffer B Input Interrupt Mask

0 = Enable Interrupt

1 = Mask Interrupt

RAMWR_A

R/W

SRAM Buffer A Input Interrupt Mask

0 = Enable Interrupt

1 = Mask Interrupt

Note1: The mask bits do not prevent the status in the ISR_0 register from being set, only from generating an

interrupt.

Table 8 - Interrupt 1 Source Register

ISR_1

(0x90- RESET=0x00)

INTERRUPT 1 SOURCE REGISTER

BIT

NAME

R/W

DESCRIPTION

ZLP_EP0

R/W

1= A ZLP has been received on EP0RX.

Reserved

This bit always reads a “0”.

ATA_PIO

This bit reflects that state of the PIO_COMPLETE bit (bit 6) of

the ATA_CTL register. It cannot be written directly.

EP1RX

R/W

1 = A Packet was successfully received on Endpoint 1 and

stored in the Buffer SRAM. OUT tokens will be NAK’d until this

bit is cleared.

EP1TX

R/W

1 = A Packet was successfully transmitted on Endpoint 1 from

the Buffer SRAM. IN tokens will be NAK’d until this bit is

cleared.

EP0RX

R/W

1 = A non-SETUP, non ZLP Packet (see ISR_0 SETUP bit)

was successfully received on Endpoint 0 and stored in the

Buffer SRAM. OUT tokens will be NAK’d until this bit is

cleared.

EP0TX

R/W

1 = A Packet was successfully transmitted on Endpoint 0 from

the Buffer SRAM. IN tokens will be NAK’d until this bit is

cleared.

SUSPEND

R/W

Suspend – If 3ms of IDLE state are detected by the hardware,

then this bit will be set.

Note 1: The bits (except for bit 5)in this register are cleared by writing a ‘1’ to the corresponding bit. If not masked by

the corresponding bit in the IMR1 mask register, a “1” on any of these bits will generate a “1” on the 8051 core’s

external INT1 input.

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