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ISP1106 Datasheet(PDF) 7 Page - NXP Semiconductors |
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ISP1106 Datasheet(HTML) 7 Page - NXP Semiconductors |
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7 / 24 page ![]() Philips Semiconductors ISP1105/1106/1107 Advanced USB transceivers Product data Rev. 06 — 30 November 2001 7 of 24 9397 750 08872 © Koninklijke Philips Electronics N.V. 2001. All rights reserved. 7.2 Operating functions [1] VP = VM = H indicates the sharing mode (VCC(5.0)/Vreg(3.3) is disconnected). [2] RCV* denotes the signal level on output RCV just before SE0 state occurs. This level is stable during the SE0 period. 7.3 Power supply configurations The ISP1105/1106/1107 can be used with different power supply configurations, which can be changed dynamically. An overview is given in Table 9. Normal mode — Both VCC(I/O) and VCC(5.0) or (VCC(5.0) and Vreg(3.3)) are connected. For 5 V operation, VCC(5.0) is connected to a 5 V source (4.0 to 5.5 V). The internal voltage regulator then produces 3.3 V for the USB connections. For 3.3 V operation, both VCC(5.0) and Vreg(3.3) are connected to a 3.3 V source (3.0 to 3.6 V). VCC(I/O) is independently connected to a voltage source (1.65 V to 3.6 V), depending on the supply voltage of the external circuit. Disable mode — VCC(I/O) is not connected, VCC(5.0) or (VCC(5.0) and Vreg(3.3)) are connected. In this mode, the internal circuits of the ISP1105/1106/1107 ensure that the (D +, D−) pins are in three-state and the power consumption drops to the low-power (suspended) state level. Some hysteresis is built into the detection of VCC(I/O) lost. Sharing mode — VCC(I/O) is connected, (VCC(5.0) and Vreg(3.3)) are not connected. In this mode, the (D +,D−) pins are made three-state and the ISP1105/1106/1107 allows external signals of up to 3.6 V to share the (D +, D−) lines. The internal circuits of the ISP1105/1106/1107 ensure that virtually no current (maximum 10 µA) is drawn via the (D +, D−) lines. The power consumption through pin V CC(I/O) drops to the Table 5: Driving function using single-ended input data interface (OE = L) [for ISP1107 and ISP1105 (MODE = L)] FSE0 VO Data L L differential logic 0 L H differential logic 1 H L SE0 H H SE0 Table 6: Driving function using differential input data interface (OE = L) [for ISP1106 and ISP1105 (MODE = H)] VMO VPO Data L L SE0 L H differential logic 1 H L differential logic 0 H H illegal state Table 7: Receiving function (OE=H) (D +, D−) RCV VP[1] VM[1] differential logic 0 L L H differential logic 1 H H L SE0 RCV*[2] LL |
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