MAX8716 datasheet(21/30 Pages) MAXIM

21 / 30 page

Interleaved High-Efficiency, Dual Power-Supply

Controllers for Notebook Computers

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Output Undervoltage Protection

If the output voltage of either SMPS falls below 70% of

its regulation voltage, the corresponding controller sets

its undervoltage fault latch, pulls PGOOD_ low, and

begins soft-shutdown for the corresponding SMPS con-

troller by pulsing DL_. DH_ remains off during the soft-

shutdown sequence initiated by an unvervoltage fault.

The other controller is not affected. After soft-shutdown

has completed, the MAX8716/MAX8717/MAX8757

force DL_ high and DH_ low. Cycle VCC below 1V or

toggle ON_ to clear the undervoltage fault latch and

restart the SMPS controller.

VCC POR and UVLO

Power-on reset (POR) occurs when VCC rises above

approximately 2V, resetting the fault latch and prepar-

ing the PWM for operation. VCC undervoltage-lockout

(UVLO) circuitry inhibits switching, forces PGOOD_

low, and forces the DL_ gate drivers low.

If VCC drops low enough to trip the UVLO comparator

while ON_ is high, the MAX8716/MAX8717/MAX8757

immediately force DH_ and DL_ low on both controllers.

The output discharges to 0V at a rate dependent on the

load and the total output capacitance. This prevents

negative output voltages, eliminating the need for a

Schottky diode to GND at the output.

Thermal Fault Protection

The MAX8716/MAX8717/MAX8757 feature a thermal

fault-protection circuit. When the junction temperature

rises above +160°C, a thermal sensor sets the fault

latches, pulls PGOOD low, and shuts down both SMPS

controllers using the soft-shutdown sequence (see the

Sort-Start and Soft-Shutdown section). Cycle VCC

below 1V or toggle ON1 and ON2 to clear the fault

latches and restart the controllers after the junction

temperature cools by 15°C.

Design Procedure

Firmly establish the input voltage range and maximum

load current before choosing a switching frequency

and inductor operating point (ripple-current ratio). The

primary design trade-off lies in choosing a good switch-

ing frequency and inductor operating point, and the fol-

lowing four factors dictate the rest of the design:

•

Input Voltage Range. The maximum value (VIN(MAX))

must accommodate the worst-case, high AC-adapter

voltage. The minimum value (VIN(MIN)) must account

for the lowest battery voltage after drops due to con-

nectors, fuses, and battery selector switches. If there

is a choice at all, lower input voltages result in better

efficiency.

•

Maximum Load Current. There are two values to

consider. The peak load current (ILOAD(MAX)) deter-

mines the instantaneous component stresses and fil-

tering requirements and thus drives output capacitor

selection, inductor saturation rating, and the design

of the current-limit circuit. The continuous load cur-

rent (ILOAD) determines the thermal stresses and

thus drives the selection of input capacitors,

MOSFETs, and other critical heat-contributing com-

ponents.

•

Switching Frequency. This choice determines the

basic trade-off between size and efficiency. The

optimal frequency is largely a function of maximum

input voltage, due to MOSFET switching losses that

are proportional to frequency and VIN2. The opti-

mum frequency is also a moving target, due to rapid

improvements in MOSFET technology that are mak-

ing higher frequencies more practical.

•

Inductor Operating Point. This choice provides

trade-offs between size vs. efficiency and transient

response vs. output ripple. Low inductor values pro-

vide better transient response and smaller physical

size, but also result in lower efficiency and higher

output ripple due to increased ripple currents. The

minimum practical inductor value is one that causes

the circuit to operate at the edge of critical conduc-

tion (where the inductor current just touches zero

with every cycle at maximum load). Inductor values

POWER-

GOOD

FAULT

0.9 x

INT REF_

1.15 x

INT REF_

0.7 x

INT REF_

FAULT

LATCH

POWER-GOOD

FAULT

PROTECTION

INTERNAL FB

TIMER

POR

Figure 7. Power-Good and Fault Protection

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