DL162 datasheet(55/128 Pages) AMD

55 / 128 page

February 6, 2004

Am42DL16x2D

AC CHARACTERISTICS

SRAM Write Cycle

Notes:

1. WE# controlled, if CIOs is low, ignore UB#s and LB#s timing.

1. tCW is measured from CE1#s going low to the end of write.

2. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CE1#s or WE# going high.

3. t

AS is measured from the address valid to the beginning of write.

4. A write occurs during the overlap (t

WP) of low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when

asserting UB#s or LB#s for a single byte operation or simultaneously asserting UB#s and LB#s for a double byte operation. A

write ends at the earliest transition when CE1#s goes high and WE# goes high. The t

WP is measured from the beginning of write

to the end of write.

Figure 30.

SRAM Write Cycle—WE# Control

Parameter

Symbol

Description

Speed Options

Unit

Write Cycle Time

Min

Chip Enable to End of Write

Min

Address Setup Time

Min

Address Valid to End of Write

Min

UB#s, LB#s to End of Write

Min

Write Pulse Time

Min

Write Recovery Time

Min

WHZ

Write to Output High-Z

Min

Max

Data to Write Time Overlap

Min

Data Hold from Write Time

Min

End Write to Output Low-Z

Min

Address

CE1#s

Data Undefined

UB#s, LB#s

WE#

Data In

Data Out

tWC

tCW

(See Note 2)

tAW

High-Z

Data Valid

CE2s

tCW

(See Note 2)

tBW

tWP

(See Note 5)

tAS

(See Note 4)

tWR (See Note 3)

tWHZ

tDW

tDH

tOW

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