DL162 datasheet(90/128 Pages) AMD

90 / 128 page

February 6, 2004

Am42DL16x2D

Enter SecSi Sector/Exit SecSi Sector

Command Sequence

The system can access the SecSi Sector region by is-

suing the three-cycle Enter SecSi Sector command

sequence. The device continues to access the SecSi

Sector region until the system issues the four-cycle

Exit SecSi Sector command sequence. The Exit SecSi

Sector command sequence returns the device to nor-

mal operation. The SecSi Sector is not accessible

when the device is executing an Embedded Program

or Embedded Erase algorithm. Table 14 shows the ad-

dress and data requirements for both command

sequences. See also “SecSi (Secured Silicon) Sector

Flash Memory Region” for further information. Note

that a hardware reset (RESET#=V

IL) will reset the de-

vice to reading array data.

Byte/Word Program Command Sequence

The system may program the device by word or byte,

depending on the state of the CIOf pin. Programming

is a four-bus-cycle operation. The program command

sequence is initiated by writing two unlock write cy-

cles, followed by the program set-up command. The

program address and data are written next, which in

turn initiate the Embedded Program algorithm. The

system is

not required to provide further controls or

timings. The device automatically provides internally

generated program pulses and verifies the pro-

grammed cell margin. Table 14 shows the address and

data requirements for the byteword program command

sequence.

When the Embedded Program algorithm is complete,

that bank then returns to reading array data and ad-

dresses are no longer latched. The system can

determine the status of the program operation by

using DQ7, DQ6, or RY/BY#. Refer to the Write Oper-

ation Status section for information on these status

bits.

Any commands written to the device during the Em-

bedded Program Algorithm are ignored. Note that a

hardware reset immediately terminates the program

operation. The program command sequence should

be reinitiated once that bank has returned to reading

array data, to ensure data integrity.

Programming is allowed in any sequence and across

sector boundaries. A bit cannot be programmed

from “0” back to a “1.” Attempting to do so may

cause that bank to set DQ5 = 1, or cause the DQ7 and

DQ6 status bits to indicate the operation was success-

ful. However, a succeeding read will show that the

data is still “0.” Only erase operations can convert a “0”

to a “1.”

Unlock Bypass Command Sequence

The unlock bypass feature allows the system to pro-

gram bytes or words to a bank faster than using the

standard program command sequence. The unlock

bypass command sequence is initiated by first writing

two unlock cycles. This is followed by a third write

cycle containing the unlock bypass command, 20h.

That bank then enters the unlock bypass mode. A

two-cycle unlock bypass program command sequence

is all that is required to program in this mode. The first

cycle in this sequence contains the unlock bypass pro-

gram command, A0h; the second cycle contains the

program address and data. Additional data is pro-

grammed in the same manner. This mode dispenses

with the initial two unlock cycles required in the stan-

dard program command sequence, resulting in faster

total programming time. Table 14 shows the require-

ments for the command sequence.

During the unlock bypass mode, only the Unlock By-

pass Program and Unlock Bypass Reset commands

are valid. To exit the unlock bypass mode, the system

must issue the two-cycle unlock bypass reset com-

mand sequence. The bank then returns to the reading

array data.

The device offers accelerated program operations

through the WP#/ACC pin. When the system asserts

HH on the WP#/ACC pin, the device automatically en-

ters the Unlock Bypass mode. The system may then

write the two-cycle Unlock Bypass program command

sequence. The device uses the higher voltage on the

WP#/ACC pin to accelerate the operation. Note that

the WP#/ACC pin must not be at V

HH any operation

other than accelerated programming, or device dam-

age may result. In addition, the WP#/ACC pin must not

be left floating or unconnected; inconsistent behavior

of the device may result.

Figure 3 illustrates the algorithm for the program oper-

at io n. R e fe r t o th e F l as h E ra se an d P r ogram

Operations table in the AC Characteristics section for

parameters, and Figure 18 for timing diagrams.

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