DL161 datasheet(55/61 Pages) AMD

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Am42DL16x4D

January 9, 2002

P R E L IMINARY

AC CHARACTERISTICS

SRAM Write Cycle

Notes:

1. WE# controlled.

2. t

CW is measured from CE1#s going low to the end of write.

3. t

WR is measured from the end of write to the address change. tWR applied in case a write ends as CE1#s or WE# going high.

4. t

AS is measured from the address valid to the beginning of write.

5. A write occurs during the overlap (tWP) of low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when

asserting UB#s or LB#s for a single byte operation or simultaneously asserting UB#s and LB#s for a double byte operation. A

write ends at the earliest transition when CE1#s goes high and WE# goes high. The t

WP is measured from the beginning of write

to the end of write.

6. If CE1# goes low (or CE2 goes high) at the same time or after WE# goes low, the outputs will remain at high impedance.

7. If CE1# goes high (or CE2 goes low) at the same time or before WE# goes high, the outputs will remain at high impedance.

8. If OE# is high during the write cycle, the outputs will remain at high impedance.

9. Output data may be present on the bus at this time; input signals should not be applied.

Figure 30.

SRAM Write Cycle—WE# Control

Parameter

Symbol

Description

Speed Options

Unit

tWC

Write Cycle Time

Min

Chip Enable to End of Write

Min

tAS

Address Setup Time

Min

Address Valid to End of Write

Min

UB#s, LB#s to End of Write

Min

tWP

Write Pulse Time

Min

Write Recovery Time

Min

tWHZ

Write to Output High-Z

Min

Max

Data to Write Time Overlap

Min

tDH

Data Hold from Write Time

Min

End Write to Output Low-Z

Min

Address

CS1#s

UB#s, LB#s

WE#

Data In

Data Out

tWC

tCW

(See Note 2)

tAW

High-Z

Data Valid

CS2s

tCW

(See Note 2)

tBW

tWP

(See Note 5)

tAS

(See Note 4)

tWR (See Note 3)

tBW

tDW

tDH

tOW

(See Note 9)

(See Note 7)

(See Note 6)

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