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M500000009 Datasheet(PDF) 42 Page - Advanced Micro Devices |
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M500000009 Datasheet(HTML) 42 Page - Advanced Micro Devices |
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42 / 63 page ![]() November 7, 2002 Am50DL128CG 41 P R E L I M I NARY FLASH AC CHARACTERISTICS Read-Only Operations Notes: 1. Not 100% tested. 2. See Figure 12 and Table 13 for test specifications 3. Measurements performed by placing a 50 Ω termination on the data pin with a bias of V CC/2. The time from OE# high to the data bus driven to V CC/2 is taken as tDF . Note: CE#f refers to active flash device being addressed (either CE#f1 or CE#f2). The chip enable input of the inactive flash device must be held high during this operation. Figure 15. Read Operation Timings Parameter Description Test Setup Speed JEDEC Std. 70 85 Unit t AVAV t RC Read Cycle Time (Note 1) Min 70 85 ns t AVQV t ACC Address to Output Delay CE#f, OE# = V IL Max 70 85 ns t ELQV t CE Chip Enable to Output Delay OE# = V IL Max 70 85 ns t GLQV t OE Output Enable to Output Delay Max 30 40 ns t EHQZ t DF Chip Enable to Output High Z (Notes 1, 3) Max 30 35 ns t GHQZ t DF Output Enable to Output High Z (Notes 1, 3) Max 30 ns t AXQX t OH Output Hold Time From Addresses, CE#f or OE#, Whichever Occurs First Min 0 ns t OEH Output Enable Hold Time (Note 1) Read Min 0 ns Toggle and Data# Polling Min 10 ns tOH tCE Outputs WE# Addresses CE#f OE# HIGH Z Output Valid HIGH Z Addresses Stable tRC tACC tOEH tRH tOE tRH 0 V RY/BY# RESET# tDF |
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