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MB2823 Datasheet(PDF) 1 Page - NXP Semiconductors |
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MB2823 Datasheet(HTML) 1 Page - NXP Semiconductors |
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1 / 10 page  Philips Semiconductors Advanced BiCMOS Products Product specification MB2823 Dual 9-bit D-type flip-flop with reset and enable (3-State) 2 August 24, 1993 853–1705 10616 FEATURES • Two sets of high speed parallel registers with positive edge-triggered D-type flip-flops • Ideal where high speed, light loading, or increased fan–in are required with MOS microprocessors • Live insertation/extraction permitted • Power-up 3-State • Power-up Reset • Output capability: +64mA/–32mA • Latch-up protection exceeds 500mA per Jedec JC40.2 Std 17 • ESD protection exceeds 2000 V per MIL STD 883 Method 3015 and 200 V per Machine Model DESCRIPTION The MB2823 dual bus interface register is designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data/address paths of buses carrying parity. The MB2823 has two 9-bit wide buffered registers with Clock Enable (nCE) and Master Reset (nMR) which are ideal for parity bus interfacing in high microprogrammed systems. The registers are fully edge-triggered. The state of each D input, one set–up time before the Low-to-High clock transition is transferred to the corresponding flip–flop’s Q output. QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS Tamb = 25°C; GND = 0V TYPICAL UNIT tPLH tPHL Propagation delay nCP to nQx CL = 50pF; VCC = 5V 4.6 ns CIN Input capacitance VI = 0V or VCC 4 pF COUT Output capacitance VO = 0V or VCC; 3-state 7 pF ICCZ Total supply current Outputs disabled; VCC = 5.5V 500 nA ORDERING INFORMATION PACKAGES TEMPERATURE RANGE ORDER CODE DRAWING NUMBER 52-Pin Plastic Quad Flat Pack –40 °C to +85°C MB2823BB 1418B PIN CONFIGURATION LOGIC SYMBOL 19 22 20 23 17 16 25 26 24 15 14 21 18 1Q7 2Q1 1Q8 2Q2 GND 1Q5 2Q4 2Q5 2Q3 1Q4 2Q0 1Q6 1Q3 1 2 3 4 5 6 7 8 9 10 11 12 13 47 44 46 43 49 50 41 40 42 51 52 45 48 1D8 2D2 2D0 GND 1D6 1D5 2D4 2D5 2D3 1D4 2D1 1D7 1D3 39 38 37 36 35 34 33 32 31 30 29 28 27 MB2823 52-Pin Quad Flat Pack 1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7 1D8 46 45 1CP 1CE 47 48 1MR 1OE 44 42 41 39 38 37 36 35 34 1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 1Q8 49 50 51 1 2 3 5 6 7 2D0 2D1 2D2 2D3 2D4 2D5 2D6 2D7 2D8 21 22 2CP 2CE 20 19 2MR 2OE 33 32 31 29 28 27 25 24 23 2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 2Q8 8 9 10 11 12 13 15 16 18 |
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