USB3250 datasheet(24/48 Pages) SMSC

24 / 48 page

USB2.0 PHY IC

Datasheet

Revision 1.5 (03-24-06)

SMSC GT3200, SMSC USB3250

DATASHEET

7.2

System Clocking

This block connects to either an external 12MHz crystal or an external clock source and generates a

480MHz multi-phase clock. The clock is used in the CRC block to over-sample the incoming received

data, resynchronize the transmit data, and is divided down to a 30MHz or 60MHz version (CLKOUT)

which acts as the system byte clock. The PLL block also outputs a clock valid signal to the other parts

of the transceiver when the clock signal is stable. All UTMI signals are synchronized to the CLKOUT

output. The behavior of the CLKOUT is as follows:

Produce the first CLKOUT transition no later than 5.6ms after negation of SUSPENDN. The

CLKOUT signal frequency error is less than 10% at this time.

The CLKOUT signal will fully meet the required accuracy of ±500ppm no later than 1.4ms after the

first transition of CLKOUT.

In HS mode there is one CLKOUT cycle per byte time. The frequency of CLKOUT does not change

when the Macrocell is switched between HS to FS modes. In FS mode (8-bit mode) there are 5 CLK60

cycles per FS bit time, typically 40 CLK60 cycles per FS byte time. If a received byte contains a stuffed

bit then the byte boundary can be stretched to 45 CLK60 cycles, and two stuffed bits would result in

a 50 CLK60 cycles.

Figure 7.1 Bidirectional 16-bit interface

DATAOUT[7:0

]

TXVALI

DATA[7:0]

DATAOUT[1

:8]

DATA[15:8]

RXVALID

VALID

DATAIN[7:0]

DATAIN[15:8]

DATAOUT[7:0

]

SELB

TXVALID

DATABUS16_

1=1

-bit mode, 0=8-bit mode

TXVALID

Transceiver

Core

USB3250 Datasheet(PDF) 24 Page - SMSC Corporation

USB3250 Datasheet(HTML) 24 Page - SMSC Corporation

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