COM20051 datasheet(45/82 Pages) SMSC

45 / 82 page

The second reception will occur as soon as a

second packet is sent to the node, as long as the

second "Enable Receive to Page fnn" command

was issued. The operation is as if a new "Enable

Receive to Page fnn" command has just been

issued.

After the first Receive status bits are

cleared, the Status Register will again be

updated with the results of the second reception

and a second interrupt resulting from the second

reception will occur.

In the ARCNET core, the Receive Inhibit (RI) bit

of the Interrupt Mask Register now masks only

the TRI bit of the Status Register, not the RI bit

as in the non-chaining mode. Since the TRI bit is

only set upon reception of a packet (not by

RESET), and since the TRI bit may easily be

reset by issuing a "Clear Receive Interrupt"

command, there is no need to use the RI bit of

the Interrupt Mask Register to mask interrupts

generated by the TRI bit of the Status Register.

In Command Chaining mode, the "Disable

Receiver"

command

will

cancel

the

oldest

reception, unless the reception has already

begun.

If both receptions should be canceled,

two "Disable Receiver" commands should be

issued.

RESET DETAILS

Internal Reset Logic

The ARCNET core supports two reset options;

software and hardware reset. A software reset is

generated when a logic "1" is written to bit 7 of

the Configuration Register. The device remains

in reset as long as this bit is set. The software

reset does not affect the contents of the Address

Pointer Registers, the Configuration Register, the

IMR, or the Setup Register. A hardware reset

occurs when a high signal is asserted on the

nRESET input. The minimum reset pulse width

is 3.2 s (for 20 MHz core clock, 1.6 s for 40 MHz

core clock) . This pulse width is used by the

internal digital filter, which filters short glitches to

allow only valid resets to occur.

Upon reset, the transmitter portion of the device

is disabled and the internal registers assume

those states outlined in the Internal Registers

section.

After the nRESET signal is removed the user

may write to the internal registers. Since writing

a non-zero value to the Node ID Register wakes

up the ARCNET core,

the

Setup Register

should be written before the Node ID Register.

Once the Node ID Register is written to, the

ARCNET core reads the value and executes two

write cycles to the RAM buffer.

Address 0 is

written with the data D1H and address 1 is

written with the Node ID. The data pattern D1H

was chosen arbitrarily, and is meant to provide

assurance of proper microsequencer operation.

INITIALIZATION SEQUENCE

When the ARCNET core is powered on the

internal registers may be written to. Since writing

a non-zero value to the Node ID Register wakes

up the core, the Setup Register should be written

to before the Node ID Register. Until a non-zero

value is placed into the NID Register, no

microcode is executed, no tokens are passed by

this node, and no reconfigurations are generated

by this node. Once a non-zero value is placed in

the register, the core wakes up, but the node will

not attempt to join the network until the TX

Enable bit of the Configuration Register is set.

Before setting the TX Enable bit, the software

may make some determinations. The software

may first observe the Receive Activity and the

Token Seen bits of the Diagnostic Status

the network.

Next, the uniqueness of the Node ID value

placed in the Node ID Register is determined.

The TX Enable bit should still be a logic "0" until

it is ensured that the Node ID is unique. If this

node ID already exists, the Duplicate ID bit of

the

Diagnostic Status Register is set after a

maximum of 840mS (or 1680mS if the ET1 and

ET2 bits are other than 1,1). To determine if

another node on the network already has this ID,

the ARCNET core compares the value in the

Node ID Register with the DID's of the token,

and determines whether there is a response to it.

Once the Diagnostic Status Register is read, the

COM20051 Datasheet(PDF) 45 Page - SMSC Corporation

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