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COM20022I-HT Datasheet(PDF) 59 Page - SMSC Corporation |
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COM20022I-HT Datasheet(HTML) 59 Page - SMSC Corporation |
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59 / 82 page  10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM Datasheet SMSC COM20022I Page 59 Revision 02-27-06 DATASHEET Chapter 8 Timing Diagrams Figure 8.1 - Multiplexed Bus, 68XX-Like Control Signals; Read Cycle AD0-AD2, VALID nCS t1 t3 t8 ALE VALID DATA t2, t6 t5 t4 t7 D3-D15 DIR t9 t10 nDS t11 t12 t13 t14 Note 2 nIOCS16 Previous Value Invalid Valid Value t15 t16 Parameter min max units t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 Address Setup to ALE Low Address Hold from ALE Low nCS Setup to ALE Low nCS Hold from ALE Low ALE Low to nDS Low nDS Low to Valid Data nDS High to Data High Impedance Cycle Time (nDS Low to Next Time Low) DIR Setup to nDS Active DIR Hold from nDS Inactive ALE High Width ALE Low Width nDS Low Width nDS High Width nIOCS16 Hold Delay from ALE Low nIOCS16 Output Delay from ALE Low 20 10 10 10 15 0 4TARB * 10 10 20 20 60 20 0 40 20 nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS MUST BE: BUSTMG pin = HIGH and RBUSTMG bit = 0 40 TARB is the Arbitration Clock Period TARB is identical to Topr if SLOW ARB = 0 * TARB is twice Topr if SLOW ARB = 1 The Microcontroller typically accesses the COM20022 on every other cycle. Therefore, the cycle time specified in the microcontroller's datasheet should be doubled when considering back-to-back COM20022 cycles. Note 1: Topr is the period of operation clock. It depends on CKUP1 and CKUP0 bits Note 2: Read cycle for Address Pointer Low/High Registers occurring after an access to Data Register requires a minimum of 5TARB from the trailing edge of nDS to the leading edge of the next nDS. Note 2 is applied to an access to Data Register by DMA transfer. |
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