ISL22326 datasheet(5/13 Pages) INTERSIL

5 / 13 page

FN6176.0

July 17, 2006

EEPROM SPECIFICATION

EEPROM Endurance

1,000,000

Cycles

EEPROM Retention

Temperature

T <55°C

Years

tWC

(Note 20)

Non-volatile Write Cycle Time

SERIAL INTERFACE SPECS

VIL

A2, A1, A0, SHDN, SDA, and SCL

Input Buffer LOW Voltage

-0.3

0.3*VCC

VIH

A2, A1, A0, SHDN, SDA, and SCL

Input Buffer HIGH Voltage

0.7*VCC

VCC+0.3

Hysteresis

SDA and SCL Input Buffer Hysteresis

0.05*

VCC

VOL

SDA Output Buffer LOW Voltage,

Sinking 4mA

00.4

Cpin

(Note 19)

A2, A1, A0, SHDN, SDA, and SCL Pin

Capacitance

fSCL

SCL Frequency

400

kHz

tsp

Pulse Width Suppression Time at

SDA and SCL Inputs

Any pulse narrower than the max spec is

suppressed

tAA

SCL falling edge to SDA output data

valid

SCL falling edge crossing 30% of VCC, until

SDA exits the 30% to 70% of VCC window

900

tBUF

Time the Bus Must be Free Before the

Start of a New Transmission

SDA crossing 70% of VCC during a STOP

condition, to SDA crossing 70% of VCC

during the following START condition

1300

tLOW

Clock LOW Time

Measured at the 30% of VCC crossing

1300

tHIGH

Clock HIGH Time

Measured at the 70% of VCC crossing

600

tSU:STA

START Condition Setup Time

SCL rising edge to SDA falling edge; both

crossing 70% of VCC

600

tHD:STA

START Condition Hold Time

From SDA falling edge crossing 30% of VCC

to SCL falling edge crossing 70% of VCC

600

tSU:DAT

Input Data Setup Time

From SDA exiting the 30% to 70% of VCC

window, to SCL rising edge crossing 30% of

VCC

100

tHD:DAT

Input Data Hold Time

From SCL rising edge crossing 70% of VCC

to SDA entering the 30% to 70% of VCC

window

0ns

tSU:STO

STOP Condition Setup Time

From SCL rising edge crossing 70% of VCC,

to SDA rising edge crossing 30% of VCC

600

tHD:STO

STOP Condition Hold Time for Read,

or Volatile Only Write

From SDA rising edge to SCL falling edge;

both crossing 70% of VCC

1300

tDH

Output Data Hold Time

From SCL falling edge crossing 30% of VCC,

until SDA enters the 30% to 70% of VCC

window

0ns

SDA and SCL Rise Time

From 30% to 70% of VCC

20 +

0.1 * Cb

250

SDA and SCL Fall Time

From 70% to 30% of VCC

20 +

0.1 * Cb

250

Capacitive Loading of SDA or SCL

Total on-chip and off-chip

400

Rpu

SDA and SCL Bus Pull-up Resistor

Off-chip

Maximum is determined by tR and tF

For Cb = 400pF, max is about 2~2.5k

Ω

For Cb = 40pF, max is about 15~20k

Ω

Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)

SYMBOL

PARAMETER

TEST CONDITIONS

MIN

TYP

(NOTE 5)

MAX

UNIT

ISL22326

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