ADF4382ABCCZ datasheet(26/70 Pages) AD

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Data Sheet

ADF4382A

THEORY OF OPERATION

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Rev. 0 | 26 of 70

Calibration Time Performance Consideration

When programming the VCO calibration time as per the VCO

Calibration section, the jitter performance can be affected by the

overall calibration time. For applications where taking a longer

time to autocalibrate is not an issue, for example, fixed frequency

applications, it is recommended to program an autocalibration time

of 250 μs to optimize jitter and phase noise performance. For oth-

er applications requiring faster autocalibration times and reduced

overall lock times, an autocalibration time of 100 μs can be used.

However, this time may degrade jitter with temperature changes

over the complete −40°C to +105°C operating range.

Table 20. Recommended Calibration Times

Autocalibration

Time (µs)

CAL_VTUNE_TO

Time

CAL_COUNT_TO

Time (µs)

CAL_VCO_TO

Time (µs)

100

Determined by the

largest loop filter

capacitor

8.5

250

Determined by the

largest loop filter

capacitor

23.5

The CAL_VTUNE_TO time is determined by the charging time of

the maximum value capacitor in the loop filter. Calculate the charge

time by using the following equation:

tCHARGE = (C × V)/I

where:

C is the largest capacitor value in loop filter.

V is the VTUNE voltage change for lock and leave over tempera-

ture, which is typically 0.8 V.

I is the VCO calibration generator current of 4.2 mA.

Core Bias Table

As part of the initialization process, the core bias table must be

programmed with the predefined values provided in Table 26 (see

mized VCO bias values for different frequency bands of operation.

After performing a device initialization, the VCO bias registers are

not reprogrammed until a subsequent power-on reset executes.

RF Output Divider (O)

A 3-bit divider, RFOUT_DIV (Register 11, Bits[7:5]), is used to

divide the frequency seen at the output buffer and feedback divider.

The divide ratio can be set to 1, 2, or 4. RFOUT_DIV is located

inside the PLL. Therefore, any change to RFOUT_DIV requires

a change to the N_INT bit fields (Register 0x010, Bits[7:0] and

the PLL losing lock for a few loop time constants.

Table 21. RFOUT_DIV Programming

RFOUT_DIV

Divisor

Output Frequency Range (GHz)

11.5 ≤ RFOUT ≤ 21

5.75 ≤ RFOUT ≤ 10.5

2.875 ≤ RFOUT ≤ 5.25

Output Invert (INV_RFOUT)

The output invert, INV_RFOUT (Register 0x011, Bit 4), is used to

shift the output signal 180°. INV_RFOUT is located inside the PLL,

and any change to INV_RFOUT results in the PLL losing lock for

few loop time constants.

Feedback Divider (N)

The feedback divider provides a division ratio in the PLL feedback

path. The division ratio consists of the N_INT (Register 0x011,

Bits[3:0] and Register 0x010, Bits[7:0]), FRAC1WORD (Register

0x15, Bit 0; Register 0x14, Bits[23:16]; Register 0x013, Bits[15:8],

and Register 0x012, Bits[7:0]), FRAC2WORD (Register 0x19,

Bits[23:16]; Register0x18, Bits[15:8]; and Register0x17, Bits[7:0]),

and MOD2WORD (Register 0x1C, Bits[23:16]; Register 0x1B,

Bits[15:8]; and Register 0x1A, Bits[7:0]) bit field values that this

divider comprises together with the fixed modulus MOD1WORD

(225). See the Applications Information section for the relation-

ship between N_INT, FRAC1WORD, MOD1WORD, FRAC2WORD,

MOD2WORD, RFOUT_DIV, together with R and D, and the fREF,

fPFD, fVCO and fOUT frequencies.

Phase Adjust

One of the following two methods can be used to perform a phase

adjustment of the RFOUT signals relative to their initial phase:

►

Bleed current mode

►

Σ-Δ mode

To enable bleed current mode, set DEL_MODE = 0. To enable Σ-Δ

mode, set DEL_MODE = 1.

Bleed Current Phase Adjustment

A small programmable constant charge pump current, known as

a bleed current, can be applied to the charge pump to adjust the

phase. Bleed current phase adjustment is used in integer mode.

Bleed current can also be applied in fractional mode to optimize

performance (see the Charge Pump Bleed Current Optimization

section for more details). The LSB step size depends on the

RFOUT frequency. PHASE_ADJ_POL determines the direction of

the phase adjustment. When PHASE_ADJ_POL = 0, the phase

value is decreased. When PHASE_ADJ_POL = 1, the phase value

is increased.

Ensure the following bit fields are programmed accordingly to

enable bleed current adjustment:

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