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ADS5527

SLWS196A – DECEMBER 2006 – REVISED MAY 2007

TIMING CHARACTERISTICS – LVDS AND CMOS MODES (continued)

For timings at lower sampling frequencies, see the Output Timing section in the APPLICATION INFORMATION of this data

sheet.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Input clock rising edge zero-cross to

tPDI

Clock propagation delay(7)

3.7

4.4

5.1

output clock rising edge zero-cross

Duty cycle of differential clock,

LVDS bit clock duty cycle

(CLKOUTP-CLKOUTM)

45%

50%

55%

≤ Fs ≤ 210 MSPS

Rise time measured from –50 mV to 50

tr ,

Data rise time,

100

200

Data fall time

Fall time measured from 50 mV to –50 mV

≤ Fs ≤ 210 MSPS

Rise time measured from –50 mV to 50

tCLKRISE,

Output clock rise time,

100

200

tCLKFALL

Output clock fall time

Fall time measured from 50 mV to –50 mV

≤ Fs ≤ 210 MSPS

Output clock jitter

Cycle-to-cycle jitter

120

ps pp

Output enable (OE) to valid data

Time to valid data after OE becomes

tOE

µs

delay

active

PARALLEL CMOS MODE

Data valid(8) to 50% of CLKOUT rising

tsu

Data setup time (5)

1.8

2.6

edge

50% of CLKOUT rising edge to data

Data hold time (9)

0.4

0.8

becoming invalid(10)

Input clock rising edge zero-cross to 50%

tPDI

Clock propagation delay(11)

2.6

3.4

4.2

of CLKOUT rising edge

Duty cycle of output clock (CLKOUT)

Output clock duty cycle

45%

≤ Fs ≤ 210 MSPS

Rise time measured from 20% to 80% of

DRVDD

tr ,

Data rise time,

Fall time measured from 80% to 20% of

0.8

1.5

2.0

Data fall time

DRVDD

≤ Fs ≤ 210 MSPS

Rise time measured from 20% to 80% of

DRVDD

tCLKRISE,

Output clock rise time,

Fall time measured from 80% to 20% of

0.4

0.8

1.2

tCLKFALL

Output clock fall time

DRVDD

≤ Fs ≤ 210 MSPS

Output enable (OE) to valid data

Time to valid data after OE becomes

tOE

delay

active

(7)

To use the input clock as the data capture clock, it is necessary to delay the input clock by a delay (tD) to get the desired setup and hold

times. Use either of these equations to calculate tD:

Desired setup time = tD - (tPDI - tsu )

Desired hold time = (tPDI + th ) - tD

(8)

Data valid refers to logic high of 2 V and logic low of 0.8 V

(9)

Setup and hold time specifications take into account the effect of jitter on the output data and clock. These specifications also assume

that the data and clock paths are perfectly matched within the receiver. Any mismatch in these paths within the receiver would appear

as reduced timing margin.

(10) Data valid refers to logic high of 2 V and logic low of 0.8 V

(11) To use the input clock as the data capture clock, it is necessary to delay the input clock by a delay (tD) to get the desired setup and hold

times. Use either of these equations to calculate tD:

Desired setup time = tD - (tPDI - tsu )

Desired hold time = (tPDI + th ) - tD

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