ADS5545 datasheet(13/57 Pages) TI

13 / 57 page

www.ti.com

DESCRIPTION OF PARALLEL PINS

SERIAL INTERFACE

ADS5527

SLWS196A – DECEMBER 2006 – REVISED MAY 2007

Table 3. SCLK Control Pin

SCLK (Pin 29)

DESCRIPTION

LOW SPEED mode Disabled - Use for sampling frequencies above 50 MSPS.

DRVDD

LOW SPEED mode Enabled - Use for sampling frequencies below 50 MSPS.

Table 4. SDATA Control Pin

SDATA (Pin 28)

DESCRIPTION

Normal operation (Default)

DRVDD

STANDBY. This is a global power down, where ADC, internal references and the output buffers are powered down.

Table 5. SEN Control Pin

SEN (Pin 27)

DESCRIPTION

CMOS mode: CLKOUT edge later by (3/12)Ts (1); LVDS mode: CLKOUT edge aligned with data transition

(1/3)DRVDD

CMOS mode: CLKOUT edge later by (2/12)Ts ; LVDS mode: CLKOUT edge aligned with data transition

(2/3)DRVDD

CMOS mode: CLKOUT edge later by (1/12)Ts ; LVDS mode: CLKOUT edge earlier by (1/12)Ts

DRVDD

Default CLKOUT position

(1)

Ts = 1/Sampling Frequency

Table 6. DFS Control Pin

DFS (Pin 6)

DESCRIPTION

2's complement data and DDR LVDS output (Default)

(1/3)DRVDD

2's complement data and parallel CMOS output

(2/3)DRVDD

Offset binary data and parallel CMOS output

DRVDD

Offset binary data and DDR LVDS output

Table 7. MODE Control Pin

MODE (Pin 23)

DESCRIPTION

Internal reference

(1/3)AVDD

External reference

(2/3)AVDD

External reference

AVDD

Internal reference

The ADC has a set of internal registers, which can be accessed through the serial interface formed by pins SEN

(Serial interface Enable), SCLK (Serial Interface Clock), SDATA (Serial Interface Data) and RESET. After device

power-up, the internal registers must be reset to their default values by applying a high-going pulse on RESET

(of width greater than 10 ns).

Serial shift of bits into the device is enabled when SEN is low. Serial data SDATA is latched at every falling edge

of SCLK when SEN is active (low). The serial data is loaded into the register at every 16th SCLK falling edge

when SEN is low. If the word length exceeds a multiple of 16 bits, the excess bits are ignored. Data is loaded in

multiples of 16-bit words within a single active SEN pulse.

The first 8 bits form the register address and the remaining 8 bits form the register data. The interface can work

with SCLK frequency from 20 MHz down to very low speeds (few Hertz) and also with non-50% SCLK duty

cycle.

Submit Documentation Feedback

ADS5545 Datasheet(PDF) 13 Page - Texas Instruments

ADS5545 Datasheet(HTML) 13 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57

Datasheet Download

Link URL