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TMS320C6421

Fixed-Point Digital Signal Processor

SPRS346B – JANUARY 2007 – REVISED APRIL 2007

Table 3-8. BOOTCMPLT Register Description (continued)

Bit

Field Name

Description

Boot Error

0000 = No Error (default).

19:16

ERR

0001 - 1111 = bootloader software detected a boot error and aborted the boot. For the error codes, see the

Using the TMS320C642x Bootloader Application Report (literature number SPRAAK5).

15:1

RESERVED Reserved. For proper device operation, the user should only write "0" to these bits.

Boot Complete Flag from Host

This field is only applicable to Host Boots.

0 = Host has not completed booting this device (default).

1 = Host has completed booting this device. DSP can begin executing from the DSPBOOTADDR register

value.

3.4.2.3 DSPBOOTADDR Register

The DSP Boot Address (DSPBOOTADDR) register contains the starting address for the C64x+ CPU.

Whenever the C64x+ is released from reset, it begins executing from the location pointed to by

DSPBOOTADDR register. For Host boots (HPI Boot), the DSPBOOTADDR register is also used for

communication between the Host and the bootloader code during boot.

The DSPBOOTADDR register is reset by any device-level global reset. For the list of device-level global

resets, see Section 6.5, Reset.

DSPBOOTADDR

R/W-0x0010 0000 or 0x4200 00000

LEGEND: R = Read; W = Write; -n = value after reset

Figure 3-4. DSPBOOTADDR Register

Table 3-9. DSPBOOTADDR Register Description

Bit

Field Name

Description

DSP Boot Address

After boot, the C64x+ CPU begins execution from this 32-bit address location

0x0010 0000 (for Internal Bootloader ROM).

0x4200 0000 (for EMIFA CS2 Space).

31:0

DSPBOOTADDR

The lower 10 bits (bits 9:0) should always be programmed to "0" as they are ignored by the

C64x+.

Default depends on boot mode selected.

See Table 3-4, Non-Fastboot Modes and Table 3-5, User-Select Multiplier Fastboot Modes.

At device reset, the Boot Controller defaults DSPBOOTADDR to one of two values (either Internal

Bootloader ROM at address 0x0010 0000 or EMIFA CS2 Space 0x4200 0000) based on the boot mode

selected (for the boot mode selections, see Table 3-4 and Table 3-5).

For Non-Host Boot Modes, software can leave the DSPBOOTADDR register at default.

For Host Boots (HPI Boot), the DSPBOOTADDR register is also used for communication between the

Host and the bootloader code during boot. For Host Boots, the DSPBOOTADDR register defaults to

Internal Bootloader ROM, and the C64x+ CPU is immediately released from reset so that it can begin

executing the bootloader code in this internal ROM. The bootloader code waits for the Host to boot the

device. Once the Host is done booting the device, it must write a new starting address into the

DSPBOOTADDR register, and follow with writing BOOTCMPLT.BC = 1 to indicate the boot is complete.

As soon as the bootloader code detects BOOTCMPLT.BC = 1, it instructs the CPU to jump to this new

DSPBOOTADDR address. At this point, the CPU continues the rest of the code execution starting from

the new DSPBOOTADDR location and the boot is completed.

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