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3.5 Configurations At Reset

3.5.1

Device and Peripheral Configurations at Device Reset

TMS320C6421

Fixed-Point Digital Signal Processor

SPRS346B – JANUARY 2007 – REVISED APRIL 2007

Some device configurations are determined at reset. The following subsections give more details.

Table 2-7, BOOT Terminal Functions, lists the device boot and configuration pins that are latched at

device reset for configuring basic device settings for proper device operation. Table 3-10 summarizes the

device boot and configuration pins, and the device functions that they affect.

Table 3-10. Default Functions Affected by Device Boot and Configuration Pins

DEVICE BOOT AND

BOOT SELECTED

PIN MUX CONTROL

GLOBAL SETTING

PERIPHERAL SETTING

CONFIGURATION PINS

BOOTMODE[3:0]

Boot Mode

PINMUX0/PINMUX1

I/O Pin Power:

PSC/Peripherals:

Registers:

Based on

BOOTMODE[3:0], the

bootloader code programs bootloader code programs

bootloader code programs VDD3P3V_PWDN register the PSC to put

PINMUX0 and PINMUX1

to power up the I/O pins

boot-related peripheral(s)

registers to select the

required for boot.

in the Enable State, and

appropriate pin functions

programs the peripheral(s)

required for boot.

for boot operation.

FASTBOOT

Fastboot

–

Sets Device Frequency:

–

Based on BOOTMODE,

FASTBOOT, and PLLMS;

the bootloader code

programs PLLC1.

PLLMS[2:0]

If FASTBOOT = 1, the

–

Sets Device Frequency:

–

PLLMS[2:0] selects the

Based on BOOTMODE,

FASTBOOT PLL

FASTBOOT, and PLLMS;

Multiplier.

the bootloader code

programs PLLC1.

AEM[2:0]

–

PINMUX0.AEM:

–

PSC/EMIFA:

Sets the default of this

The EMIFA module state

field to control the EMIFA

defaults to SwRstDisable

Pinout Mode.

if AEM = 0; otherwise, the

EMIFA module state

Affects the pin muxing in

defaults to Enable.

EMIFA Sub-Block 0, 1,

and 3.

LENDIAN

–

Device endianess

–

For proper device operation, external pullup/pulldown resistors may be required on these device boot and

configuration pins. For discussion situations where external pullup/pulldown resistors are required, see

Section 3.9.1, Pullup/Pulldown Resistors.

Note: The C6421 configuration inputs (BOOTMODE[3:0], FASTBOOT, PLLMS[2:0], AEM[2:0], and

LENDIAN) are multiplexed with other functional pins. These pins function as device boot and configuration

pins only during device reset. The user must take care of any potential data contention in the system. To

help avoid system data contention, the C6421 puts these configuration pins into a high-impedance state

(Hi-Z) when device reset (RESETor POR) is asserted, and continues to hold them in a high-impedance

state until the internal global reset is removed; at which point, the default peripheral (either GPIO or

EMIFA based on default of AEM[2:0]) will now control these pins.

All of the device boot and configuration pin settings are captured in the corresponding bit fields in the

BOOTCFG register (see Section 3.4.2.1, BOOTCFG Register).

The following subsections provide more details on the device configurations determined at device reset:

AEM, PLLMS, and LENDIAN.

Device Configurations

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