TMS320C6421 datasheet(192/227 Pages) TI

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TMS320C6421

Fixed-Point Digital Signal Processor

SPRS346B – JANUARY 2007 – REVISED APRIL 2007

Table 6-50. McASP0 Data Registers

HEX ADDRESS RANGE

ACRONYM

COMMENTS

(Used when RBUSEL or

McASP0 receive buffers or McASP0 transmit buffers via

XBUSEL bits = 0 [these bits are

01D0 1400 – 01D0 17FF

RBUF/XBUF

the Peripheral Data Bus.

located in the RFMT or XFMT

registers, respectively].)

6.14.1.3

McASP0 Electrical Data/Timing

6.14.1.3.1

Multichannel Audio Serial Port (McASP) Timing

Table 6-51. Timing Requirements for McASP (see Figure 6-34 and Figure 6-35)

(1)

-400

-500

NO.

UNIT

-600

MIN

MAX

tc(AHCKRX)

Cycle time, AHCLKR/X

tw(AHCKRX)

Pulse duration, AHCLKR/X high or low

tc(CKRX)

Cycle time, ACLKR/X(2)

ACLKR/X ext

tw(CKRX)

Pulse duration, ACLKR/X high or low

ACLKR/X ext

ACLKR/X int

tsu(FRX-CKRX)

Setup time, AFSR/X input valid before ACLKR/X latches data

ACLKR/X ext

ACLKR/X int

th(CKRX-FRX)

Hold time, AFSR/X input valid after ACLKR/X latches data

ACLKR/X ext

ACLKR/X int

tsu(AXR-CKRX)

Setup time, AXR input valid before ACLKR/X latches data

ACLKR/X ext

ACLKR/X int

th(CKRX-AXR)

Hold time, AXR input valid after ACLKR/X latches data

ACLKR/X ext

(1)

ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1

ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0

ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1

ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1

ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0

ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1

(2)

There is a clock ratio requirement between the system infrastructure clock, SYSCLK3, and the McASP0 bit clocks, ACLKR/ACLKX. For

proper device operation, the ACLKR/ACLKX frequency must be no faster than ½ of SYSCLK3 frequency.

Peripheral Information and Electrical Specifications

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