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UCD7230 Datasheet(PDF) 14 Page - Texas Instruments |
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UCD7230 Datasheet(HTML) 14 Page - Texas Instruments |
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14 / 33 page ![]() www.ti.com To A/D A0 5 BLANK DLY t ( ns ) R ( k ) » W 1 2 CS CS ( in ) DLY R V . R + æ ö = ´ ç ÷ è ø 10 LIM CS ( out ) I V = UCD7230 SLUS741C – NOVEMBER 2006 – REVISED MARCH 2007 APPLICATION INFORMATION (continued) The amp output can go up to 3.3 V, so reasonable designs limits full scale to 3.0 V. Should attenuation be necessary, use a resistive divider between AO and the control chip A/D input as shown in Figure 7. Figure 7. Attenuating and Filtering the Voltage Representation of the Average Output Current While the current sense amplifier is useful for accurate current monitoring or controlling overload conditions, extreme overload conditions must be handled in timeframes that are generally much shorter than the A/D of a control chip can achieve. Therefore, there are two comparators on the UCD7230 to sense extreme overload and protect the driven power MOSFETs. Extreme current overload is handled in two ways by the UCD7230. One is a comparator that monitors the voltage between POS and NEG, or effectively the output current of the converter.. The other is a comparator that monitors the voltage drop across the high-side MOSFET, or effectively the input current. Should either condition exceed a preset value, OUT1 is immediately turned off for the remainder of the cycle. To program the current limit, a value of resistance from DLY to AGND must first be chosen to establish a blanking time during which the comparators will be blinded to switching noise. The blanking time starts with the rising edge on IN for the input comparator and from both the rising and falling edge of IN for the output comparator. Blanking time is given by: where RDLY is the resistor from DLY to AGND. RDLY should be limited to a range of 25 kΩ to 100 kΩ. Once RDLY has been chosen, the threshold for the input comparator, i.e., the drop allowed across the high-side MOSFET, is given by: Where VCS(in) is the threshold of allowed voltage across the high-side MOSFET and RCS+ is a resistor connected from CS+ to the drain of the high-side MOSFET. The blanking time for the output comparator is identical to the input comparator. The output comparator threshold is given by: where VCS(out) is the threshold of allowed voltage between the POS and NEG pins and ILIM is the voltage on the ILIM pin. Note that the ILIM is internally connected to 0.5 V through a 42 k Ω resistor. Any voltage between 0.25 V and 1.0 V can be applied to ILIM. For voltages above 1.0 V, the maximum VCS(OUT) threshold is clamped to 0.1 V. Possible methods for setting ILIM are shown in Figure 8. When using the output comparator to monitor the voltage on the parallel sensing capacitor across the inductor, the same caveats apply as described for the current sense amplifier. 14 |
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