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AM2732 Datasheet(PDF) 85 Page - Texas Instruments |
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AM2732 Datasheet(HTML) 85 Page - Texas Instruments |
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85 / 114 page ![]() 7 Detailed Description 7.1 Overview The AM273x is a high performance microcontroller with an integrated C66x DSP and is ideally suited for applications needing requiring conditioning and processing functions. Two R5F cores (with optional lockstep capability) running at 400 MHz with 5MB of internal memory coupled along with a broad range of automotive and industrial connectivity peripherals and an easy to use SDK enables our customers to address a wide range of use cases in automotive and industrial markets. Functional safety and security (HSM) features are integrated to address emerging market trends. One representative use case is for the AM273x to operate as the MCU host in an automotive radar system. In this role AM273x provides data aggregation, FFT, CFAR, range, velocity and angle estimation and tracking processing. The AM273x can operate as a host in single or dual (cascaded) front-end radar application. As seen in Figure 3-1 the AM273x is divided into a few high level functional subsystems. Each subsystem contains specific control, signal processing, and digital communication peripherals. • Main Subsystem (MSS): MCU Core, Cryptographic Core, Mailbox, EDMA, RTI, QSPI, SPI, CAN-FD, I2C, UART, Ethernet and GPIO • DSP Subsystem (DSS): C66x Core, HWA2.0 Accelerator, Mailbox, EDMA, RTI • Radar Controller Subsystem (RCSS): EDMA, CSI2A/B, SPIA/B, I2C and GPIO Each primary subsystem is then interconnected through an ECC enabled, switch interconnect bus, allowing for EDMA transfer of data between peripherals and processing cores. 7.2 Main Subsystem The main subsystem (MSS) is the primary controller of the device and controls all the other device subsystem cores and peripherals. The MSS contains the Cortex-R5F (MSS R5F) processor and associated peripherals and associated EDMA and Mailbox IPC functions. The MSS also controls wider system connectivity and network peripherals such as the I2C, UART, SPI, CAN-FD, EPWM, and Ethernet. The MSS is connected to the primary interconnect through the Main Subsystem (MSS) Interconnect which is ECC enabled. The MSS contrains its own dedicated functional safety block consisting of DCC, ESM, LBIST/PBIST, CRC Watchdog Timer and GPADC for safety monitoring of critical system signals such as power supply and temperature monitors. 7.3 DSP Subsystem The DSP subsystem (DSS) contains the TI high performance C66x DSP, HWA 2.0, and a high-bandwidth interconnect for high performance (128-bit, 150MHz), and associated data transfer peripherals: 6x EDMA for data transfer, 2x RTI and Mailbox IPC. The Aurora/LVDS measurement data output interface is also mastered by the C66x DSP. L3 shared memory is available on the DSS interconnect which is also ECC enabled. For more information on DSP functionality, see the 7.4 Radar Control Subsystem The radar control subsystem (RCSS) integrates a high-bandwidth interconnect with a pair of 4-lane, CSI 2.0 receivers (CSI2_RX0 and CSI2_RX1), two SPI controllers (RCSS_SPIA and RCSS_SPIB), I2C controllers and a set of GPIO. The SPI, I2C and GPIO peripherals can be utilized for controlling and configuring the attached sensor devices. The CSI 2.0 receivers allow for receiveing high-speed sensor data samples such as samples. Within the device pinlist there are also a number of pins which have been named in support of a radar front-end connection use-case. All of these signals resolve to various MSS/RCSS GPIO functionality in the device pinmux and therefore do not exist in the list of pinmux signal. See the below description of these signals. www.ti.com AM2732, AM2732-Q1 SWRS245B – DECEMBER 2021 – REVISED DECEMBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 85 Product Folder Links: AM2732 AM2732-Q1 |
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