Datasheet

14

002-37216 Rev. *B

2023-10-10

EZ-PD™ PAG2S-QZ integrated USB PD and secondary-side QR-ZVS

controller

Functional description

Figure 8

PWM_DRV in CCM mode

PAG2S-QZ also supports zero voltage switching where in it turns on the SR_GDRV for a short duration before

driving PWM_DRV, as shown in Figure 9. This is meant to pull the primary drain voltage low, thereby ensuring

zero voltage switching. ZVS pulse width is firmware configurable, thereby enabling optimization for each design.

Figure 9

ZVS in DCM mode

Ramp

Error Amplifier Output

Time

Primary current

Primary FET drain

voltage

Secondary current

PWM_DRV

Primary FET ON,

SR FET OFF

Primary FET OFF,

SR FET ON

SR_SEN

Time

Primary FET drain

voltage

PWM_DRV

SR_SEN

SR_GDRV

ZVS pulse