Datasheet

15

002-37216 Rev. *B

2023-10-10

EZ-PD™ PAG2S-QZ integrated USB PD and secondary-side QR-ZVS

controller

Functional description

Analog PWM smart algorithm allows the operation to automatically transition between modes based on the

output power requirement. The mode of operation stays in CrCM for higher loads, moves to DCM for medium

loads, and switches to skip mode or burst mode for low and ultra-low power loads (see Figure 10).

Figure 10

Error amplifier output vs modes of operation

3.4

Fault protection

3.4.1

VBUS OVP, UVP, OCP, and SCP

VBUS undervoltage and overvoltage faults are monitored using internal VBUS_IN/VBUS_C resistor dividers. VBUS

overcurrent and short-circuit faults are monitored using internal current sense amplifiers (CSA). The fault

thresholds and response mechanisms are firmware-configurable.

3.4.2

Overtemperature protection

Over-temperature monitoring is done using an external thermistor and internal ADC. The thermistor can be

connected to any free GPIO. PAG2S-QZ has an integrated 8-bit SAR ADC, which is available for general purpose

analog-to-digital conversions. The fault thresholds and response mechanisms are firmware-configurable.

3.4.3

ESD, CC OVP, and DP/DM OVP

PAG2S-QZ offers ESD protection on all pins. Further, the chip integrates protection against accidental short of CC

pins to the high-voltage VBUS_C rail and also protects against overvoltage on DP/DM pins.

3.5

Power modes

PAG2S-QZ supports multiple power modes - Active, Sleep, and Deep Sleep. Transitions between these modes is

handled by the application firmware depending on the operating conditions.

3.6

MCU subsystem

PAG2S-QZ integrates a 32-bit Cortex®-M0+ MCU with 64-KB flash, 8-KB SRAM, and 64-KB ROM. PAG2S-QZ also

supports 1x TCPWM and 2x ADC.

Time

Skip entry

Skip exit, Burst entry

Burst exit

DCM (Valley)

Skip

Burst

Skip

Burst

DCM (Valley)