ADP2102 datasheet(3/7 Pages) AD

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Preliminary Technical Data

ADP2102

Rev. PrA| Page 3 of 7

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter

Rating

AVIN,EN,MODE,FB/OUT to AGND

−0.3V to +6V

LX to PGND

−0.3V to +(VIN + 0.3 V)

PVIN to PGND

−0.3V to +6V

PGND to AGND

−0.3V to 0.3V

AVIN to PVIN

-0.3V to 0.3V

Operating Ambient Temperature Range

−40°C to +85°C1

Operating Junction Temperature

125°C

Storage Temperature Range

−65°C to +150°C

Soldering Conditions

JEDEC J-STD-020

1 In applications where high power dissipation and poor thermal resistance

are present, the maximum ambient temperature may have to be de-rated.

Maximum ambient temperature (TA(MAX)) is dependent on the maximum

operating junction temperature (TJ(MAXOP)) = 125°C), the maximum power

dissipation of the device (PD(MAX)), and the junction-to-ambient thermal

resistance of the part/package in the application (θJA), using the following

equation: TA(MAX) = TJ(MAXOP) – (θJA x PD(MAX)).

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Absolute maximum ratings apply individually only, not in

combination. Unless otherwise specified all other voltages

referenced to GND.

THERMAL RESISTANCE

Table 3. Thermal Resistance

Package Type

θJA1

Unit

8-Lead LFCSP

°C/W

Maximum Power Dissipation

1 Junction-to-ambient thermal resistance (θJA) of the package is based on

modeling and calculation using a 4-layer board. The junction-to-ambient

thermal resistance is application and board-layout dependent. In

applications where high maximum power dissipation exists, attention to

thermal board design is required. The value of θJA can vary depending on

PCB material, layout, and environmental conditions. For more information,

please refer to Application Note AN-772: A Design and Manufacturing Guide

for the Lead Frame Chip Scale Package (LFCSP).

BOUNDARY CONDITION

Natural convection, 4-layer board, exposed pad soldered to the PCB.

ESD CAUTION

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