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AD9937KCPRL Datasheet(PDF) 5 Page - Analog Devices |
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AD9937KCPRL Datasheet(HTML) 5 Page - Analog Devices |
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5 / 44 page  AD9937 –5– REV. 0 TIMING SPECIFICATIONS (C L = 20 pF, AVDD = DVDD = DRVDD = 3 V, fCLI = 12 MHz, unless otherwise noted.) CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9937 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. ABSOLUTE MAXIMUM RATINGS With Respect Parameter To Min Max Unit AVDD AVSS –0.3 +3.9 V TCVDD TCVSS –0.3 +3.9 V HVDD HVSS –0.3 +3.9 V RSVDD RSVSS –0.3 +3.9 V DVDD DVSS –0.3 +3.9 V DRVDD DRVSS –0.3 +3.9 V RS Output RSVSS –0.3 RSVDD + 0.3 V H1(A–D), H2(A, B)Output HVSS –0.3 HVDD + 0.3 V Digital Outputs DVSS –0.3 DVDD + 0.3 V Digital Inputs DVSS –0.3 DVDD + 0.3 V SCK, SLD, SDA DVSS –0.3 DVDD + 0.3 V VRT, VRB AVSS –0.3 AVDD + 0.3 V CCDIN AVSS –0.3 AVDD + 0.3 V Junction Temperature 150 °C Lead Temperature, 10 sec 350 °C ORDERING GUIDE Temperature Package Package Model Range Description Option AD9937KCP –25 °C to +85°CLead Frame CP-56 Chip Scale Package (LFCSP) AD9937KCPRL –25 °C to +85°CLead Frame CP-56 Chip Scale Package (LFCSP) Parameter Symbol Min Typ Max Unit MASTER CLOCK, VCKM VCKM Clock Period tCONV 83.33 ns VCKM High/Low Pulsewidth 41.67 ns Delay from VCKM Rising Edge to Internal Pixel Position 0 tVCKMDLY 9ns AFE CLAMP PULSES 1 CLPOB Pulsewidth 2 220Pixels AFE SAMPLE LOCATION 1 (See Figure 13) SHP Sample Edge to SHD Sample Edge tS1 33.34 41.67 ns DATA OUTPUTS Output Delay from VCLK Rising Edge tOD 9ns Pipeline Delay from SHP/SHD Sampling (See Figure 40) 9 Cycles SERIAL INTERFACE Maximum SCK Frequency fSCLK 10 MHz SLD to SCK Setup Time tLS 10 ns SCK to SLD Hold Time tLH 10 ns SDA Valid to SCK Rising Edge Setup tDS 10 ns SCK Falling Edge to SDA Valid Hold tDH 10 ns SCK Falling Edge to SDA Valid Read tDV 10 ns NOTES 1Parameter is programmable. 2Minimum CLPOB pulsewidth is for functional operation only. Wider typical pulses are recommended to achieve good clamp performance. Specifications subject to change without notice. PACKAGE THERMAL CHARACTERISTICS Thermal Resistance JA = 24.9 °C/W |
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