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AD9937KCPRL Datasheet(PDF) 24 Page - Analog Devices |
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AD9937KCPRL Datasheet(HTML) 24 Page - Analog Devices |
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24 / 44 page ![]() REV. 0 –24– AD9937 P[0] PIXEL PERIOD RS H1 P[48] = P[0] SHP[24] CCD SIGNAL P[24] P[12] P[36] SHD[48] POSITION CDS (INTERNAL) tS1 RSf[12] RSr[0] Hr[0] Hf[24] Figure 14. High Speed Clock Default and Programmable Locations FIXED CROSSOVER VOLTAGE H1 H2 tPD < tRISE H2 H1 tRISE tPD Figure 15. H-Clock Inverse Phase Relationship 1. DOUTPHASE REGISTER (ADDR 0x05) CAN BE USED TO SHIFT THE PHASE OF VCLK AND DOUT TOGETHER WITH RESPECT TO P[0]. 2. DOUT[9:0] CAN BE INDEPENDENTLY DELAYED WITH RESPECT TO VCLK BY USING DOUT_DELAY REGISTER (ADDR 0x05). P[0] P[48] = P[0] PIXEL PERIOD P[12] P[24] P[36] DOUT VCLK tOD Figure 16. Digital Output Phase Adjustment |
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