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4901A–RKE–11/05

ATA3745

5.3

Bit Check Mode

In bit check mode, the incoming data stream is examined to distinguish between a valid signal

from a corresponding transmitter and signals due to noise. This is done by subsequent time

frame checks where the distances between 2 signal edges are continuously compared to a pro-

grammable time window. The maximum count of this edge-to-edge test, before the receiver

switches to receiving mode, is also programmable.

5.3.1

Configuring the Bit Check

Assuming a modulation scheme that contains 2 edges per bit, two time frame checks verify one

bit. This is valid for Manchester, Bi-phase and most other modulation schemes. The maximum

count of bits to be checked can be set to 0, 3, 6 or 9 bits via the variable N

register. This implies 0, 6, 12 and 18 edge-to-edge checks respectively. If N

higher value, the receiver is less likely to switch to the receiving mode due to noise. In the pres-

ence of a valid transmitter signal, the bit check takes less time if N

In polling mode, the bit check time is not dependent on N

example where 3 bits are tested successfully and the data signal is transferred to pin DATA.

Figure 5-4 shows that the time window for the bit check is defined by two separate time limits. If

the edge-to-edge time t

limit T

the bit check will be terminated and the receiver switches to sleep mode.

Figure 5-4.

Valid Time Window for Bit Check

For best noise immunity it is recommended to use a low span between T

This is achieved using a fixed frequency at a 50% duty cycle for the transmitter preburst. A

“11111...” or a “10101...” sequence in Manchester or Bi-phase is a good choice in this regard. A

good compromise between receiver sensitivity and susceptibility to noise is a time window of

±25% regarding the expected edge-to-edge time t

ous edge-to-edge time periods, the bit check limits must be programmed according to the

required span.

The bit check limits are determined by means of the formulas below:

T

T

Lim_min and Lim_max are defined by a 5-bit word each within the LIMIT register.

Using the above formulas, Lim_min and Lim_max can be determined according to the required

T

minimum edge-to-edge time t

on page 15. Due to this, the lower limit should be set to Lim_min

≥ 10. The maximum value of

the upper limit is Lim_max = 63.

Dem_out

t

ee

T

Lim_max

1/f

Sig

T

Lim_min