Philips Semiconductors

Product data

PCK111

Low voltage 1:10 differential

PECL clock driver

2

2001 Sep 07

853-2281 27052

FEATURES

DESCRIPTION

The PCK111 is a low skew 1-to-10 differential driver, designed with

clock distribution in mind. It accepts two clock sources into an input

multiplexer. The PECL input signals can be either differential or

out to 10 identical differential outputs.

The PCK111 is specifically designed, modeled and produced with

low skew as the key goal. Optimal design and layout serve to

minimize gate-to-gate skew within a device, and empirical modeling

is used to determine process control limits that ensure consistent

guaranteed low skew device.

To ensure that the tight skew specification is met, it is necessary that

both sides of the differential output are terminated into 50

Ω, even if

only one side is being used. In most applications, all ten differential

pairs will be used, and therefore terminated. In the case where fewer

than ten pairs are used, it is necessary to terminate at least the

output pairs on the same package side as the pair(s) being used on

that side, in order to maintain minimum skew. Failure to do this will

result in small degradations of propagation delay (on the order of

10–20 ps) of the output(s) being used, which, while not being

catastrophic to most designs, will mean a loss of skew margin.

The PCK111 can be used for high performance clock distribution in

+3.3 V or +2.5 V systems. Designers can take advantage of the

PCK111’s performance to distribute low skew clocks across the

backplane or the board. In a PECL environment, series or Thevenin

line terminations are typically used as they require no additional

power supplies.

output with the CLK0 input. If a single-ended signal is to be used,

ground via a 0.01

0.2 mA, therefore, it should be used as a switching reference for the

PCK111 only. Part-to-part skew specifications are not guaranteed

when driving the PCK111 single-endedly.

PINNING

Pin configuration

24

23

22

21

20

19

18

17

Q3

Q3

Q4

Q4

Q5

Q5

Q6

Q6

1

2

3

4

5

6

7

8

PCK111

SW00907

CLK_SEL

CLK0

CLK0

CLK1

CLK1

Figure 1. Pin configuration

Pin description

SYMBOL

PIN

DESCRIPTION

1

Supply voltage

CLK_SEL

2

Active clock select input

CLK0, CLK0

3, 4

Differential ECL/PECL input pair

5

CLK1, CLK1

6, 7

Differential HSTL input pair

8

Ground

9, 16, 25, 32

Output drive power supply

voltage

Q0–Q9

31, 29, 27, 24,

22, 20, 18, 15,

13, 11

Differential PECL outputs

Q0–Q9

30, 28, 26, 23,

21, 19, 17, 14,

12, 10

Differential PECL outputs

ORDERING INFORMATION

Type n mber

Package

Temperature

Type number

Name

Description

Version

p

range

PCK111BD

LQFP32

plastic low profile quad flat package; 32 leads; body 7

× 7 × 1.4 mm

SOT358-1

–40 to +70

°C