ACT41000 datasheet(39/72 Pages) QORVO

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ACT41000

Programmable Voltage, Programmable Current, Low Noise

RFPoL Step-Down Voltage Regulator

Main-buck Regulator

The main-buck is the main step-down switching regulator of the ACT41000 device.

Figure 58. Main-buck Regulator

At a very high level, the SW pin (switching) node voltage is filtered by the output LC filter to have the output voltage. Then,

the output voltage is fed back to the FB_VO input to close the regulator control loop.

The main-buck block requires following external components.

• An output LC filter. See Main-buck LC Output Filter.

• A bootstrap capacitor. See Main-buck Bootstrap Capacitor.

• A compensation capacitor. See Main-buck Compensation Network.

• A current limit programming resistor. See Programmable Current Limit.

• A current sense register. See Output Current Sensing.

Main-buck Enable Control

The main-buck regulator is enabled and disabled by this enable control block. From the view point of power sequencing, the

input of the main-buck is the iEN signal from this block and the output is the Main-buck Power-Good signal.

Disable.

When iEN is logic-L, the main-buck is disabled.

The main-buck provides an active discharge function when the Reg09[4] bit is logic-H. During the active discharge, the

device activates the Output Discharge Resistor to force the output near ground level in shorter time. This feature is useful in

applications where the output is expected to start from the (near) ground voltage.

When the Reg09[4] bit is logic-L, the main-buck makes the output node high impedance at it disabled condition.

Consumption current from load devices discharges the output and, generally, the output voltage value is uncontrolled.

Enable.

When iEN is logic-H, the main-buck is enabled and it regulates the output as described in following sections.

No Controller to Drive the EN pin.

The EN pin has an internal pull-up source as shown in the Figure 59, so the EN pin becomes logic-H by leaving it open

(connected to nothing) and the main-buck gets enabled every time the Control Logic comes to the Bias Ready status.

By using an external delay circuit, the device can support an application specific needs in many flexible ways. See Timing

Control between PGBIAS and EN.

EN Input Buffer

The logic input buffer at the EN pin provides a programmable hysteresis capability. As shown in the Figure 59, There are

two of 1-µA current sources at the EN pin where the first 1-µA element is always connected working as a constant bias and

the second 1-µA element gets connected to the EN pin when its input is logic-H as a hysteresis source.

ACT41000 Data Sheet, Rev. B, 01-Apr-2022

Subject to change without notice

ACT41000 Datasheet(PDF) 39 Page - Qorvo, Inc