Si5326

2

Confidential Rev. 0.2

Table 1. Performance Specifications

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Temperature Range

–40

25

85

ºC

Supply Voltage

2.97

3.3

3.63

V

2.25

2.5

2.75

V

1.62

1.8

1.98

V

Supply Current

Both CKOUTs enabled

LVPECL format output

—251

279

mA

CKOUT2 disabled

—

217

243

mA

Both CKOUTs enabled

CMOS format output

—204

234

mA

CKOUT2 disabled

—

194

220

mA

Tristate/Sleep Mode

—

TBD

TBD

mA

Input Clock Frequency

(CKIN1, CKIN2)

Input frequency and clock

multiplication ratio deter-

mined by programming

device PLL dividers. Con-

sult Silicon Laboratories con-

figuration software

DSPLLsim to determine PLL

divider settings for a given

input frequency/clock multi-

plication ratio combination.

0.002

—

710

MHz

Output Clock Frequency

(CKOUT1, CKOUT2)

0.002

970

1213

—945

1134

1417

MHz

Input Clocks (CKIN1, CKIN2)

Differential Voltage Swing

0.25

—

1.9

VPP

Common Mode Voltage

1.8 V ±10%

0.9

—

1.4

V

2.5 V ±10%

1.0

—

1.7

V

3.3 V ±10%

1.1

—

1.95

V

Rise/Fall Time

20–80%

—

—

11

ns

Duty Cycle

Whichever is less

40

—

60

%

50

—

—

ns

Output Clocks (CKOUT1, CKOUT2)

Common Mode

LVPECL

100

Ω load

line-to-line

—

V

Differential Output Swing

1.1

—

1.9

Single Ended Output

Swing

0.5

—

0.93

V

Rise/Fall Time

20–80%

—

230

350

ps

Note: For a more comprehensive listing of device specifications, please consult the Silicon Laboratories Any-Rate Precision

Clock Family Reference Manual. This document can be downloaded from www.silabs.com/timing.