Si5326

Confidential Rev. 0.2

3

Duty Cycle

45

—

55

%

PLL Performance

Jitter Generation

LVPECL output format

50 kHz–80 MHz

—

0.3

TBD

ps rms

12 kHz–20 MHz

—

0.3

TBD

ps rms

800 Hz–80 MHz

—

TBD

TBD

ps rms

Jitter Transfer

—

0.05

0.1

dB

External Reference Jitter

Transfer

—TBD

TBD

dB

Phase Noise

100 Hz offset

—

TBD

TBD

dBc/Hz

1 kHz offset

—

TBD

TBD

dBc/Hz

10 kHz offset

—

TBD

TBD

dBc/Hz

100 kHz offset

—

TBD

TBD

dBc/Hz

1 MHz offset

—

TBD

TBD

dBc/Hz

Subharmonic Noise

set

—

TBD

TBD

dBc

Spurious Noise

Max spur @ n x F3

(n > 1, n x F3 < 100 MHz)

—

TBD

TBD

dBc

Package

Thermal Resistance

Junction to Ambient

Theta JA

Still Air

—

TBD

—

ºC/W

Table 2. Absolute Maximum Ratings

Parameter

Symbol

Value

Unit

DC Supply Voltage

–0.5 to 3.6

V

LVCMOS Input Voltage

V

Operating Junction Temperature

–55 to 150

ºC

Storage Temperature Range

–55 to 150

ºC

ESD HBM Tolerance (100 pF, 1.5 k

Ω)2

kV

ESD MM Tolerance

200

V

Latch-Up Tolerance

JESD78 Compliant

Note: Permanent device damage may occur if the Absolute Maximum Ratings are exceeded. Functional operation should be

restricted to the conditions as specified in the operation sections of this data sheet. Exposure to absolute maximum

rating conditions for extended periods of time may affect device reliability.

Table 1. Performance Specifications (Continued)

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Note: For a more comprehensive listing of device specifications, please consult the Silicon Laboratories Any-Rate Precision