ADC3683 datasheet(58/70 Pages) TI1

58 / 70 page

Figure 9-10. Register 0x19

FCLK SRC

FCLK DIV

TOG FCLK

R/W-0

Table 9-11. Register 0x19 Field Descriptions

Bit

Field

Type

Reset

Description

FCLK SRC

R/W

User has to select if FCLK signal comes from ADC or from DDC

block. Here real decimation is treated same as bypass mode

0: FCLK generated from ADC. FCLK SRC set to 0 for DDC

bypass, real decimation mode and 1/2-w complex decimation

mode.

1: FCLK generated from DDC block. In complex decimation

mode only this bit needs to be set for 2-w and 1-w output

interface mode but NOT for 1/2-w mode.

6-5

R/W

Must write 0

FCLK DIV

R/W

This bit needs to be set to 1 for 2-w output mode in bypass/real

decimation mode only .

0: All output interface modes except 2-w decimation bypass and

real decimation mode.

1: 2-w output interface mode for decimation bypass and real

decimation.

3-1

R/W

Must write 0

TOG FCLK

R/W

This bit adjusts the FCLK signal appropriately for 1/2-wire mode

where FCLK is stretched to cover channel A and channel B.

This bit ONLY needs to be set in 1/2-wire mode with complex

decimation mode.

0: all other modes.

1: FCLK for 1/2-wire complex decimation mode.

Table 9-12. Configuration of FCLK SRC and FCLK DIV Register Bits vs Serial Interface

BYPASS/DECIMATION

SERIAL INTERFACE

FCLK SRC

FCLK DIV

TOG FCLK

Decimation Bypass/ Real Decimation

2-wire

1-wire

1/2-wire

Complex Decimation

2-wire

1-wire

1/2-wire

ADC3683-SP

SBASAB5 – MARCH 2024

www.ti.com

Submit Document Feedback

Product Folder Links: ADC3683-SP

ADC3683 Datasheet(PDF) 58 Page - Texas Instruments

ADC3683 Datasheet(HTML) 58 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70

Datasheet Download

Link URL