Electronic Components Datasheet Search
  English  ▼

X  

ADC3683 Datasheet(PDF) 10 Page - Texas Instruments

Click here to check the latest version.
Part # ADC3683
Description  ADC3683-SP Space Grade 18-Bit 1 to 65MSPS, Low Noise, Ultra-low Power Dual Channel ADC
PDF  70 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

ADC3683 Datasheet(HTML) 10 Page - Texas Instruments

Back Button ADC3683 Datasheet HTML 6Page - Texas Instruments ADC3683 Datasheet HTML 7Page - Texas Instruments ADC3683 Datasheet HTML 8Page - Texas Instruments ADC3683 Datasheet HTML 9Page - Texas Instruments ADC3683 Datasheet HTML 10Page - Texas Instruments ADC3683 Datasheet HTML 11Page - Texas Instruments ADC3683 Datasheet HTML 12Page - Texas Instruments ADC3683 Datasheet HTML 13Page - Texas Instruments ADC3683 Datasheet HTML 14Page - Texas Instruments Next Button
Zoom Inzoom in Zoom Outzoom out
 10 / 70 page
background image
5.8 Timing Requirements
Typical values are at TA = 25°C, MIN and MAX timing values are characterized over the full temperature range TMIN = –55°C
to TMAX = 105°C and are NOT production tested, ADC sampling rate = 65 MSPS, 50% clock duty cycle, AVDD = IOVDD =
1.8 V, 1.6 V external reference, and –1-dBFS differential input, unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN NOM
MAX
UNIT
ADC Timing Specifications
tAD
Aperture Delay
0.85
ns
tA
Aperture Jitter
Square wave clock with fast edges
180
fs
tJ
Jitter on DCLKIN
±
50 (1)
ps
tACQ
Signal acquisition period, referenced
to sampling clock falling edge
FS = 10 Msps
-TS/2
Sampling
Clock
Period
FS = 25 Msps
-TS/2
FS = 65 Msps
-TS/4
tCONV
Signal conversion period, referenced
to sampling clock falling edge
FS = 10 Msps
+TS ×
1/5
Sampling
Clock
Period
FS = 25 Msps
+TS ×
3/8
FS = 65 Msps
+TS ×
5/8
Wake up
time
Time to valid data after coming out of
power down. Internal reference.
Bandgap reference enabled, single ended clock
us
Bandgap reference enabled, differential clock
Bandgap reference disabled, single ended clock
ms
Bandgap reference disabled, differential clock
Time to valid data after coming out of
power down.
External 1.6V reference.
Bandgap reference enabled, single ended clock
us
Bandgap reference enabled, differential clock
100
Bandgap reference disabled, single ended clock
ms
Bandgap reference disabled, differential clock
tS,SYNC
Setup time for SYNC input signal
Referenced to sampling clock rising edge
500
ps
tH,SYNC
Hold time for SYNC input signal
600
ADC
Latency
Signal input to data output
SLVDS 2-wire
2
ADC
clock
cycles
SLVDS 1-wire
1
SLVDS 1/2-wire
1
Add
Latency
Real decimation by 2
21
Output
clock
cycles
Complex decimation by 2
22
Real or complex decimation by 4, 8, 16, 32
23
ADC3683-SP
SBASAB5 – MARCH 2024
www.ti.com
10
Submit Document Feedback
Copyright © 2024 Texas Instruments Incorporated
Product Folder Links: ADC3683-SP



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com