Over recommended operating supply and temperature ranges unless otherwise specified.

Symbol

Parameter

Conditions

Pin/Freq.

Min

Typ

Max

Units

LVDS DC SPECIFICATIONS

V

OD

Output Differential Voltage

(D

R

Ω, w/o Pre-emphasis

VODSEL = L

(VODSEL = H) (Figure 16)

Tx: D

250

(450)

400

(750)

600

(1200)

mV

∆V

OD

Output Differential Voltage

Unbalance

R

Ω, w/o Pre-emphasis

10

50

mV

V

OS

Offset Voltage

R

Ω, w/o Pre-emphasis

1.00

1.25

1.50

V

∆V

OS

Offset Voltage Unbalance

R

Ω, w/o Pre-emphasis

1

50

mV

I

OS

Output Short Circuit Current

DOUT = 0V, DIN = H,

TPWDNB, DEN = 2.4V,

VODSEL = L

−2

−8

mA

DOUT = 0V, DIN = H,

TPWDNB, DEN = 2.4V,

VODSEL = H

−7

−13

mA

I

OZ

TRI-STATE Output Current

TPWDNB, DEN = 0V,

DOUT = 0V or 2.4V

−15

+15

µA

SER/DES SUPPLY CURRENT (DVDD*, PVDD* and AVDD* pins) *Digital, PLL, and Analog VDDs

I

CCT

Serializer (Tx)

Total Supply Current

(includes load current)

R

Ω

R

VODSEL = H/L

Checker-board pattern (Figure 1)

f=35MHz

40

65

mA

R

Ω

R

Ω

VODSEL = H/L

Checker-board pattern (Figure 1)

f=35MHz

45

70

mA

Serializer (Tx)

Total Supply Current

(includes load current)

R

Ω

R

VODSEL = H/L

f=35MHz

40

65

mA

R

Ω

R

Ω

VODSEL = H/L

Random pattern

f=35MHz

45

70

mA

I

CCTZ

Serializer (Tx)

Supply Current Power-down

TPWDNB = 0V

(All other LVCMOS Inputs = 0V)

800

µA

I

CCR

Deserializer (Rx)

Total Supply Current

(includes load current)

C

Checker-board pattern

(Figure 2)

f=35MHz

75

mA

Deserializer (Rx)

Total Supply Current

(includes load current)

C

Random pattern

f=35MHz

50

mA

I

CCRZ

Deserializer (Rx)

Supply Current Power-down

RPWDNB = 0V

(All other LVCMOS Inputs = 0V,

R

50

µA

Serializer Timing Requirements for TCLK

Over recommended operating supply and temperature ranges unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Units

t

TCP

Transmit Clock Period

(Figure 6)

28.6

T

200

ns

t

TCIH

Transmit Clock High Time

0.4T

0.5T

0.6T

ns

t

TCIL

Transmit Clock Low Time

0.4T

0.5T

0.6T

ns

t

CLKT

TCLK Input Transition Time

(Figure 5)3

6

ns

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