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DS90C124 Datasheet(PDF) 4 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor. Click here to check the latest version.
Part # DS90C124
Description  5-35MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer
PDF  21 Pages
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Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

DS90C124 Datasheet(HTML) 4 Page - National Semiconductor (TI)

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Serializer Timing Requirements for TCLK (Continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
t
JIT
TCLK Input Jitter
(Note 9)
33
ps
(RMS)
Serializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
t
LLHT
LVDS Low-to-High Transition Time
R
L = 100
Ω, (Figure 3)
C
L =10pFtoGND
VODSEL = L
0.6
ns
t
LHLT
LVDS High-to-Low Transition Time
0.6
ns
t
DIS
DIN (23:0) Setup to TCLK
R
L = 100
Ω,
C
L =10pFtoGND
(Note 8)
5ns
t
DIH
DIN (23:0) Hold from TCLK
5ns
t
HZD
DOUT ± HIGH to TRI-STATE Delay
R
L = 100
Ω,
C
L =10pFtoGND
(Figure 7) (Note 4)
15
ns
t
LZD
DOUT ± LOW to TRI-STATE Delay
15
ns
t
ZHD
DOUT ± TRI-STATE to HIGH Delay
200
ns
t
ZLD
DOUT ± TRI-STATE to LOW Delay
200
ns
t
PLD
Serializer PLL Lock Time
R
L = 100
Ω, (Figure 8)10
ms
t
SD
Serializer Delay
R
L = 100
Ω, (Figure 9)
VODSEL = L, TRFB = H
3.5T + 2.85
3.5T
+10
ns
R
L = 100
Ω, (Figure 9)
VODSEL = L, TRFB = L
3.5T + 2.85
3.5T
+10
ns
TxOUT_E_O
TxOUT_Eye_Opening
(respect to ideal)
5–35 MHz
(Figure 14)
(Notes 8, 9, 13)
0.75
UI
(Note 10)
Deserializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Pin/Freq.
Min
Typ
Max
Units
t
RCP
Receiver out Clock Period
t
RCP =tTCP
(Note 8)
RCLK
28.6
200
ns
t
RDC
RCLK Duty Cycle
RCLK
45
50
55
%
t
CLH
LVCMOS Low-to-High
Transition Time
C
L =8pF
(lumped load)
(Figure 4)
ROUT [23:0],
LOCK, RCLK
2.5
3.5
ns
t
CHL
LVCMOS High-to-Low
Transition Time
2.5
3.5
ns
t
ROS
ROUT (7:0) Setup Data to
RCLK (Group 1)
(Figure 11)
ROUT [7:0]
(0.40)*
t
RCP
(29/56)*t
RCP
ns
t
ROH
ROUT (7:0) Hold Data to
RCLK (Group 1)
(0.40)*
t
RCP
(27/56)*t
RCP
ns
t
ROS
ROUT (15:8) Setup Data to
RCLK (Group 2)
(Figure 11)
ROUT [15:8],
LOCK
(0.40)*
t
RCP
0.5*t
RCP
ns
t
ROH
ROUT (15:8) Hold Data to
RCLK (Group 2)
(0.40)*
t
RCP
0.5*t
RCP
ns
t
ROS
ROUT (23:16) Setup Data to
RCLK (Group 3)
(Figure 11)
ROUT [23:16]
(0.40)*
t
RCP
(27/56)*t
RCP
ns
t
ROH
ROUT (23:16) Hold Data to
RCLK (Group 3)
(0.40)*
t
RCP
(29/56)*t
RCP
ns
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