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DS90C124 Datasheet(PDF) 5 Page - National Semiconductor (TI) |
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DS90C124 Datasheet(HTML) 5 Page - National Semiconductor (TI) |
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5 / 21 page ![]() Deserializer Switching Characteristics (Continued) Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Pin/Freq. Min Typ Max Units t HZR HIGH to TRI-STATE Delay (Figure 12) ROUT [23:0], RCLK, LOCK 310 ns t LZR LOW to TRI-STATE Delay 3 10 ns t ZHR TRI-STATE to HIGH Delay 3 10 ns t ZLR TRI-STATE to LOW Delay 3 10 ns t DD Deserializer Delay (Figure 10) RCLK [4+(3/56)]T +5.9 [4+(3/56)]T +14 ns t DRDL Deserializer PLL Lock Time from Powerdown (Figure 13) (Notes 7, 8) 5 MHz 5 50 ms 35 MHz 5 50 ms RxIN_TOL_L Receiver INput TOLerance Left, (Figure 15) (Notes 6, 8, 10) 5 MHz–35 MHz 0.25 UI RxIN_TOL_R Receiver INput TOLerance Right, (Figure 15) (Notes 6, 8, 10) 5 MHz–35 MHz 0.25 UI Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation. Note 2: Typical values are given for VCC = 3.3V and TA = +25˚C. Note 3: Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground except VOD, ∆VOD, VTH and VTL which are differential voltages. Note 4: When the Serializer output is tri-stated, the Deserializer will lose PLL lock. Resynchronization MUST occur before data transfer. Note 5: tDRDL is the time required by the deserializer to obtain lock when exiting powerdown mode. tDRDL is specified with an external synchronization pattern. Note 6: RxIN_TOL is a measure of how much phase noise (jitter) the deserializer can tolerate in the incoming data stream before bit errors occur. It is a measurement in reference with the ideal bit position, please see National’s AN-1217 for detail. Note 7: The Deserializer PLL lock time (tDRDL) may vary depending on input data patterns and the number of transitions within the pattern. Note 8: Parameter is guaranteed by design and characterization using statistical analysis. Note 9: tJIT (@BER of 10e-9) specifies the allowable jitter on TCLK. tJIT not included in TxOUT_E_O parameter. Note 10: UI – Unit Interval, equivalent to one ideal serialized data bit width. The UI scales with frequency. Note 11: Figures 1, 2, 9, 10, 13 show a falling edge data strobe (TCLK IN/RCLK OUT). Note 12: Figures 6, 11 show a rising edge data strobe (TCLK IN/RCLK OUT). Note 13: TxOUT_E_O is affected by pre-emphasis value. www.national.com 5 |
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