TMF8801 datasheet(14/73 Pages) OSRAM

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TMF8801

Functional Description

Datasheet

• PUBLIC

DS000648

• v10-00 • 2022-Dec-20

│ 13

Functional Description

7.1

I²C Protocol

The TMF8801 is controlled by an I²C bus, one interrupt pin and two GPIO pins.

The device uses I²C serial communication protocol for communication. The device supports 7-bit chip

addressing and standard, fast mode and fast mode plus modes. Read and Write transactions comply

with the standard set by Philips (now NXP). For a complete description of the I²C protocol, please

review the NXP I²C design specification.

Internal to the device, an 8-bit buffer stores the register address location of the byte to read or write.

This buffer auto-increments upon each byte transfer and is retained between transaction events (i.e.

valid even after the master issues a STOP and the I²C bus is released). During consecutive Read

transactions, the future/repeated I²C Read transaction may omit the memory address byte normally

following the chip address byte; the buffer retains the last register address +1.

A Write transaction consists of a START, CHIP-ADDRESSWRITE, REGISTER-ADDRESSWRITE,

DATA BYTE(S), and STOP. Following each byte (9TH clock pulse) the slave places an

ACKNOWLEDGE/NOT- ACKNOWLEDGE (ACK/NACK) on the bus. If NACK is transmitted by the

slave, the master may issue a STOP.

A Read transaction consists of a START, CHIP-ADDRESSWRITE, REGISTER-ADDRESS,

RESTART, CHIP-ADDRESSREAD, DATA BYTE(S), and STOP. Following all but the final byte the

master places an ACK on the bus (9TH clock pulse). Termination of the Read transaction is indicated

by a NACK being placed on the bus by the master, followed by STOP.

The default I²C address is 0x41. The address can be changed after power-up. Use the enable pin to

enable only one device at a time to provide unique device addresses.

7.2

System Parameters

The on-chip microprocessor is a Cortex M0 µP.

TMF8801 Datasheet(PDF) 14 Page - OSRAM GmbH