ams Datasheet

Page 15

[v1-08] 2017-Aug-28

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TSL2584TSV − Register Description

Control Register (00h)

The Control Register is used primarily to power the device up

and down as shown in Figure 17.

Figure 17:

Control Register.

Note(s):

1. ADC_EN and POWER must be asserted before the ADC changes will operate correctly. After POWER is asserted, a 2-ms delay is

required before asserting ADC_EN.

2. The device registers should be configured before ADC_EN is asserted.

76

5

4

3

2

1

0

Reserved

ADC_INTR

ADC_VALID

Reserved

ADC_EN

POWER

Field

Bits

Description (Reset - 00h)

Reserved

7:6

Reserved. Write as 0.

ADC_INTR

5

ADC Interrupt. Read only. Indicates that the device is asserting an interrupt.

ADC_VALID

4

ADC Valid. Read only. Indicates that the ADC Channel has completed an

integration cycle.

Reserved

3:2

Reserved. Write as 0.

ADC_EN

1

ADC Enable. This field enables the two ADC Channels to begin integration.

Writing a 1 activates the ADC Channels, and writing a 0 disables the ADCs.

POWER

0

Power On. Writing a 1 powers on the device, and writing a 0 turns it off.