TSL2584TSVM datasheet(18/34 Pages) OSRAM

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[v1-08] 2017-Aug-28

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TSL2584TSV − Register Description

Interrupt Register (02h)

The Interrupt Register controls the extensive interrupt

capabilities of the device. The open-drain interrupt pin is active

low and requires a pull-up resistor to VDD in order to pull high

in the inactive state. The Interrupt Register provides control

over when a meaningful interrupt will occur. The concept of a

meaningful change can be defined by the user both in terms of

light intensity and time, or persistence of that change in

intensity. The value must cross the threshold (as configured in

the Threshold Registers 03h through 06h) and persist for some

period of time as outlined in Figure 19.

When a level Interrupt is selected, an interrupt is generated

whenever the last conversion results in a value outside of the

programmed threshold window. The interrupt is active-low and

remains asserted until cleared by writing an 11 in the

TRANSACTION field in the COMMAND register.

Figure 19:

Interrupt Control Register

Note(s):

1. Interrupts are based on the value of Channel 0 only.

2. Use this bit to isolate a particular condition when the sensor is continuously integrating.

Reserved

INTR_STOP

INTR

PERSIST

Field

Bits

Description (Reset = 00h)

Reserved

Reserved. Write as 0.

INTR_STOP (2)

Stop ADC Integration on Interrupt. When high, ADC integration will stop

once an interrupt is asserted. To resume operation (1) de-assert ADC_EN

using CONTROL register, (2) clear interrupt using COMMAND register, and (3)

re-assert ADC_EN using CONTROL register.

INTR

5:4

INTR Control Select. This field determines mode of interrupt logic according

to Figure 20, below.

PERSIST

3:0

Interrupt Persistence. Controls rate of interrupts to the host processor as

shown in Figure 21, below.

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