56F8323 datasheet(84/140 Pages) FREESCALE

84 / 140 page

56F8323 Technical Data, Rev. 17

Freescale Semiconductor

Preliminary

6.3 Operating Modes

Since the SIM is responsible for distributing clocks and resets across the chip, it must understand the

various chip operating modes and take appropriate action. These are:

•

Reset Mode, which has two submodes:

— Total Reset Mode

– 56800E Core and all peripherals are reset

— Core-Only Reset Mode

– 56800E Core in reset, peripherals are active

– This mode is required to provide the on-chip Flash interface module time to load data from Flash

into FM registers.

•

Run Mode

The primary mode of operation for this device, in which the 56800E controls chip operation

•

Debug Mode

56800E is controlled via JTAG/EOnCE when in debug mode. All peripherals, except the COP and PWMs,

continue to run. COP is disabled and PWM outputs are optionally switched off to disable any motor from

being driven; see the PWM chapter in the 56F8300 Peripheral User Manual for details.

•

Wait Mode

In Wait mode, the core clock and memory clocks are disabled. Optionally, the COP can be stopped.

Similarly, it is an option to switch off PWM outputs to disable any motor from being driven. All other

peripherals continue to run.

•

Stop Mode

56800E, memory, and most peripheral clocks are shut down. Optionally, the COP and CAN can be stopped.

For lowest power consumption in Stop mode, the PLL can be shut down. This must be done explicitly before

entering Stop mode, since there is no automatic mechanism for this. The CAN (along with any non-gated

interrupt) is capable of waking the chip up from Stop mode, but is not fully functional in Stop mode.

6.4 Operating Mode Register

Figure 6-1 OMR

The reset state for MB will depend on the Flash secured state. See Part 4.2 and Part 7 for detailed

information on how the Operating Mode Register (OMR) MA and MB bits operate in this device. The EX

bit is not functional in this device since there is no external memory interface. For all other bits, see the

56F8300 Peripheral User Manual.

Note:

The OMR is not a Memory Map register; it is directly accessible in code through the acronym OMR.

Bit

Type

R/W

RESET

0000

56F8323 Datasheet(PDF) 84 Page - Freescale Semiconductor, Inc

56F8323 Datasheet(HTML) 84 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL