56F8323 datasheet(97/140 Pages) FREESCALE

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Clock Generation Overview

56F8323 Technical Data, Rev. 17

Freescale Semiconductor

Preliminary

6.5.10.2

Input/Output Short Address Low (ISAL[21:6])—Bit 15–0

This field represents the lower 16 address bits of the “hard coded” I/O short address.

6.6 Clock Generation Overview

The SIM uses an internal master clock from the OCCS (CLKGEN) module to produce the peripheral and

system (core and memory) clocks. The maximum master clock frequency is 120MHz. Peripheral and

system clocks are generated at half the master clock frequency and therefore at a maximum 60MHz. The

SIM provides power modes (Stop, Wait) and clock enables (SIM_PCE register, CLK_DIS, ONCE_EBL)

to control which clocks are in operation. The OCCS, power modes, and clock enables provide a flexible

means to manage power consumption.

Power utilization can be minimized in several ways. In the OCCS, the relaxation oscillator, crystal

oscillator, and PLL may be shut down when not in use. When the PLL is in use, its prescaler and postscaler

can be used to limit PLL and master clock frequency. Power modes permit system and/or peripheral clocks

to be disabled when unused. Clock enables provide the means to disable individual clocks. Some

peripherals provide further controls to disable unused subfunctions. Refer to Part 3 On-Chip Clock

Synthesis (OCCS), and the 56F8300 Peripheral User Manual for further details.

The memory, peripheral and core clocks all operate at the same frequency (60MHz max).

6.7 Power-Down Modes

The 56F8323/56F8123 operate in one of three power-down modes, as shown in Table 6-2

All peripherals, except the COP/watchdog timer, run off the IPBus clock frequency, which is the same as

the main processor frequency in this architecture. The maximum frequency of operation is SYS_CLK =

60MHz.

Refer to the PCE register in Part 6.5.9 and ADC power modes. Power is a function of the system

frequency, which can be controlled through the OCCS.

Table 6-2 Clock Operation in Power-Down Modes

Mode

Core Clocks

Peripheral Clocks

Description

Run

Active

Device is fully functional

Wait

Core and memory

clocks disabled

Active

Peripherals are active and can produce

interrupts if they have not been masked off.

Interrupts will cause the core to come out of its

suspended state and resume normal operation.

Typically used for power-conscious applications.

Stop

System clocks continue to be generated in

the SIM, but most are gated prior to

reaching memory, core and peripherals.

The only possible recoveries from Stop mode

are:

1. CAN traffic (1st message will be lost)

2. Non-clocked interrupts (IRQA)

3. COP reset

4. External reset

5. Power-on reset

56F8323 Datasheet(PDF) 97 Page - Freescale Semiconductor, Inc

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